Memory With Internal Processors Reducing External Bus Power
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Solution Overview
Problem
The processing efficiency of electronic systems is limited by the bandwidth of external buses, leading to increased power consumption and processing time due to the need for external communication between processors and memory arrays.
Innovation Solution
Incorporating internal processors, such as arithmetic logic units (ALUs), directly within the memory device, allowing for reduced external communication and processing power consumption by enabling the memory to execute instructions with minimal external assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is accessed via external bus between processor and memory array, then communication bandwidth is maintained, but processing speed is limited and power consumption increases
Solution Approach 1:
The patent combines the processor and memory array into a single integrated device, allowing the processor to execute instructions directly within the memory structure. This merging eliminates the need for external bus communication, thereby increasing processing speed and reducing power consumption associated with data transfer between separate components.
Solution Approach 2:
The patent introduces an internal bus structure as an intermediary within the memory device, allowing high-speed data transfer between the processor and memory array without requiring external bus communication. This internal intermediary enables faster processing while reducing the power consumption of external communication interfaces.
2Productivity
If processor is external to memory array, then system architecture is simplified, but processing efficiency is reduced due to external communication requirements
Solution Approach 1:
The patent merges the processor and memory array into a single integrated device, improving processing efficiency by eliminating external communication requirements. While this increases internal complexity, it resolves the contradiction by demonstrating that the performance benefits outweigh the architectural complexity through unified control logic and integrated design.
3Productivity
If multiple instructions are executed through ALU circuitry, then computational capability is improved, but communication overhead with external memory increases
Solution Approach 1:
The patent integrates the ALU circuitry within the memory device, allowing multiple instructions to be executed without external communication overhead. The processor can directly access and manipulate data within the memory array, eliminating the time loss associated with external data transfer while maintaining high computational capability.
Solution Approach 2:
The patent implements preliminary action by pre-fetching and buffering data within the memory device before external access is required. This allows computational operations to be performed on data already present in the integrated memory structure, reducing communication overhead time while maintaining high computational throughput.
Data Source
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AI summary
Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.