Memory Internal Processors Parallel Data Transfer
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Solution Overview
Problem
Existing memory systems are limited by the bandwidth of external buses, which restricts processing efficiency and power conservation when transferring information between processors and memory arrays.
Innovation Solution
Incorporating internal processors, such as ALUs, directly into memory devices, allowing for simultaneous writing, reading, sequencing, buffering, and executing of instructions and data without the need for an external bus, thereby enhancing pipelining and processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred between processor and memory array via external bus, then device complexity is reduced, but processing speed and power efficiency deteriorate due to bandwidth limitations
Solution Approach 1:
The patent merges the processor and memory array into a single integrated device, with the processor physically coupled to the memory array within the same device package. This integration eliminates the external bus interface, allowing direct data transfer between the processor and memory array, thereby achieving higher processing speed and power efficiency while maintaining acceptable device complexity through unified architecture design.
2Productivity
If processor is external to memory array, then ease of manufacture is improved, but processing performance deteriorates due to bus bandwidth constraints
Solution Approach 1:
The processor and memory array are integrated into a single device with direct internal coupling, eliminating external bus dependencies and enabling high-performance data transfer. This integration achieves superior processing performance while remaining manufacturable through standard semiconductor fabrication processes that can produce multi-component integrated devices.
3Productivity
If internal processors are integrated into memory device, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The processor is integrated within the memory device package with direct coupling to the memory array, enabling efficient data transfer and processing. The complexity is managed through a unified device architecture where the processor and memory array function as an integrated system rather than separate components, achieving high processing efficiency while maintaining reasonable device complexity.
Solution Approach 2:
The integrated device performs multiple functions including data storage in the memory array and data processing in the processor, both within a single device package. This multi-functionality improves processing efficiency by eliminating data transfer bottlenecks while the shared device structure helps manage overall complexity.
Data Source
AI summary
Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).