Semiconductor Memory Internal Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices consume excessive current by maintaining high driving force and generating internal voltages unnecessarily after data input/output operations are completed, leading to inefficient power usage.
Innovation Solution
Implementing an internal voltage generating circuit with stepwise-varying driving forces by using first and second enable signals with distinct activation timings to control subsets of internal voltage generators, reducing unnecessary current consumption by adjusting driving forces based on the operational state of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal voltage generating circuit maintains high driving force after data operations are completed, then the voltage level stability is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the driving force of the internal voltage generating circuit adjustable rather than fixed. The circuit transitions between different operating states (first and second driving forces) based on operational requirements, allowing it to adapt its power consumption characteristics to match the actual workload and timing requirements.
Solution Approach 2:
The patent implements periodic action by using sequentially activated enable signals (first enable signal and second enable signal) to control the internal voltage generating circuit. The circuit operates with high driving force during critical periods (immediate post-operation) and reduces to low driving force during extended periods, creating a time-based operational pattern that balances stability and power consumption.
2Speed
If the internal voltage generating circuit uses high driving force continuously, then the voltage generation speed is improved, but the current consumption increases
Solution Approach 1:
The patent applies partial action by providing high driving force only when necessary (immediately after data operations) rather than continuously. The first enable signal activates the high-driving-force path for a limited duration, and the second enable signal provides extended coverage with reduced driving force, ensuring voltage generation completes without unnecessary energy expenditure.
Solution Approach 2:
The circuit dynamically adjusts its driving force based on the operational phase. During critical voltage transition periods, high driving force is applied for fast voltage generation. During extended periods where voltage maintenance is sufficient, the circuit switches to low driving force mode, optimizing the balance between speed and energy loss.
3Device complexity
If the internal voltage generating circuit operates with predetermined driving force, then the circuit design is simplified, but the power efficiency decreases
Solution Approach 1:
The patent segments the internal voltage generating circuit into multiple paths with different driving force characteristics. One path is configured for high driving force operation, another for low driving force operation. Enable signals selectively activate appropriate paths based on operational requirements, allowing the circuit to optimize power efficiency without excessive complexity through modular organization.
Solution Approach 2:
The internal voltage generating circuit is designed with multi-functionality by incorporating both high-driving-force and low-driving-force paths within a single unified structure. The same basic voltage generation mechanism serves dual purposes depending on which enable signal is active, reducing overall circuit complexity while maintaining power efficiency through functional versatility.
Data Source
AI summary
Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the active command, and the second enable signal being deactivated after a second time longer than the first time from the deactivation timing of the active command. Internal voltage generators are configured to generate internal voltages. At least one of the internal voltage generators is turned on/off in response to the first enable signal, and at least one other of the internal voltage generators is turned on/off in response to the second enable signals.