Semiconductor Memory Device Interrupt Handling via Status Data Counting
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Solution Overview
Problem
Semiconductor memory devices face inefficiencies during program and erase operations, particularly when interrupt instructions are inputted, as existing systems lack effective mechanisms to manage the progress and interruption of these operations efficiently.
Innovation Solution
A semiconductor memory device with a memory cell array, peripheral circuit for generating program and erase voltages, and control logic for counting pulse numbers and storing status data, allowing for continuous or interrupted operations based on the status data in response to interrupt instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt instructions are handled during program and erase operations, then responsiveness to external requests is improved, but operation management complexity increases
Solution Approach 1:
The control logic pre-prepares status data that reflects the current state of program and erase operations before interrupts occur. This preliminary preparation of status information allows the system to quickly respond to interrupt instructions without complex real-time analysis, thereby improving responsiveness while managing complexity through advance preparation of operational state data.
Solution Approach 2:
The system implements feedback mechanisms where the control logic continuously monitors and updates status data regarding program and erase operation progress. This feedback loop enables the system to make informed decisions when interrupt instructions are received, allowing efficient operation management by providing real-time operational state information that simplifies interrupt handling logic.
2Measurement precision
If program and erase operations are continuously monitored, then operation control precision is improved, but processing overhead increases
Solution Approach 1:
The control logic monitors program and erase operations at strategically selected intervals rather than continuously, updating status data at key progression points. This partial monitoring approach maintains sufficient operation control precision to make informed interrupt handling decisions while significantly reducing processing overhead and energy consumption compared to continuous monitoring.
Solution Approach 2:
The system employs periodic status data updates during program and erase operations, where the control logic checks operation progress at regular intervals rather than continuously. This periodic monitoring maintains adequate precision for operation control while minimizing processing overhead by allowing the system to enter low-power states between monitoring cycles.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data.