Memory Word Inversion Bits for FRAM Imprint Reliability
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Solution Overview
Problem
Imprint, a reliability concern in new memory types such as FRAM, where memory cells retain a remnant data state over time, leading to difficulty in distinguishing between data states like '0' and '1', affects the performance and functionality of memory arrays.
Innovation Solution
A method is introduced to reduce imprint by adding an additional bit, the inversion condition bit, associated with memory bits in a memory array. This bit is toggled selectively using control circuitry, allowing the memory data states to change without altering the output, thereby maintaining data integrity and reducing imprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are used in new memory types (FRAM, MRAM, PRAM) to achieve higher density and lower power consumption, then performance and energy efficiency are improved, but imprint reliability issues arise causing data state distinction to fail over time
Solution Approach 1:
The memory word is segmented into payload bits and an associated inversion condition bit stored in a first memory location, with an inversion status bit in a second memory location. This segmentation allows the inversion condition bit to track and compensate for imprint effects on individual memory words without affecting other words.
Solution Approach 2:
The inversion condition bit acts as an intermediary that mediates between the physical memory cells and the data interpretation logic. By toggling this bit based on imprint compensation algorithms, the system can correct data state distinctions without physically altering the memory cells themselves.
2Reliability
If memory cells remain in the same data state over long periods to maintain data, then data integrity is preserved, but imprint effects accumulate causing remnant polarization that degrades reliability
Solution Approach 1:
The system performs periodic toggling of the inversion condition bit and associated memory bits at intervals determined by the address counter wrapping around. This periodic action prevents imprint accumulation by regularly inverting data states, while the inversion status bit ensures that memory operations remain available during these periodic updates.
Solution Approach 2:
The invention changes the parameter of data state representation by introducing inversion condition bits that alter how data is interpreted rather than physically changing storage density or cell structure. This allows the same physical memory cells to maintain data while compensating for imprint through logical parameter changes.
3Reliability
If additional inversion condition bits and control circuitry are added to reduce imprint, then reliability is improved, but device complexity and memory overhead increase
Solution Approach 1:
The inversion condition bit is merged with the existing memory word structure in the first memory location, and the inversion status bit is integrated into the second memory location. This merging approach incorporates imprint compensation functionality into the existing memory architecture rather than adding completely separate control circuits, thereby reducing overall device complexity.
Solution Approach 2:
The inversion condition bit and inversion status bit serve multiple functions: they track imprint conditions, control data inversion, and maintain memory availability. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby minimizing the increase in device complexity while achieving reliable imprint compensation.
Data Source
AI summary
One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.