Memory I/O Driving Circuit for 3.3 V Interface Reliability
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Solution Overview
Problem
Existing IO circuits using CMOSFETs with medium or thin gate oxides for low-supply voltage operations fail to function properly when a voltage of 3.3 V is applied, necessitating a solution to support 3.3 V interface voltage requirements.
Innovation Solution
The proposed interface system includes an input/output driving circuit with a pull-down driver and gate control logic, featuring a series of NMOS and PMOS transistors. The gate control logic generates a feedback voltage to control the first NMOS transistor, ensuring reliable operation even at 3.3 V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOSFETs with medium or thin gate oxides are used for low-supply voltage operations, then power consumption is reduced and operating speed is improved, but the circuit fails to function properly when 3.3 V is applied
Solution Approach 1:
The patent introduces a level shift circuit as an intermediary component between the low-voltage CMOSFET-based IO circuit and the 3.3 V interface. This level shift circuit converts the 3.3 V input signal to a voltage level suitable for the CMOSFET operation (1.8 V or 0.9 V), enabling the circuit to interface with 3.3 V devices while maintaining reliable operation of the low-voltage transistors.
2Adaptability or versatility
If a voltage of 3.3 V is applied to the pad, then compatibility with application circuits is achieved, but the IO circuit using medium or thin gate oxide CMOSFETs cannot work properly
Solution Approach 1:
The patent segments the voltage interface into two distinct parts: the pad interface section that handles 3.3 V signals and the internal circuit section that operates at low voltage (1.8 V or 0.9 V). The level shift circuit acts as the boundary between these segments, allowing each segment to operate at its optimal voltage level independently.
3Speed
If the clock signal transitions rapidly, then high-speed operation is achieved, but the voltage difference between pad and node may exceed acceptable limits
Solution Approach 1:
The patent employs a feedback mechanism where the level shift circuit continuously monitors the voltage at the pad and adjusts its output accordingly. When the clock signal transitions cause the pad voltage to change rapidly, the feedback mechanism ensures that the voltage difference between the pad and internal nodes remains within acceptable limits, preventing unreliable operation.
Data Source
AI summary
A memory system may include a memory device and a memory controller. The memory device may be configured to store data. The memory controller may be configured to communicate with the memory device by an input/output driving circuit. The input/output driving circuit comprises a pull-down driver and a gate control logic. The pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. The gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. The source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.