Memory I/O Line Error Correction Using BCH Symbol Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in error correction, particularly when a single input/output (IO) line fails, leading to 4-bit errors, and previous approaches often attempt to correct the entire error, which is not reliable and wastes resources.
Innovation Solution
Implementing a linked-interface (LK-IF) architecture where pairs of bits are communicated via each IO line, allowing for effective error correction using Bose-Chaudhuri-Hocquenghem (BCH) error correction codes, reducing the number of bits required for error correction and enabling their reuse for other purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used to correct 4-bit errors from a failed IO line, then error correction capability is provided, but resource efficiency deteriorates and reliability is insufficient
Solution Approach 1:
The patent segments the error correction problem by identifying that only 2 out of 4 bits need correction when an IO line fails. Instead of correcting all 4 bits, the method divides the correction task into essential (2 bits) and non-essential (2 bits) portions, thereby improving resource efficiency while maintaining sufficient reliability.
Solution Approach 2:
The patent applies partial action by performing only the necessary 2-bit correction instead of the traditional 4-bit correction. This partial correction approach provides sufficient error correction capability for system reliability while conserving computational resources and reducing overhead.
2Reliability
If bits are used for error correction, then error correction is achieved, but available bits for other purposes decrease
Solution Approach 1:
The patent segments the bit usage into error correction bits (2 bits) and reusable bits (2 bits). This segmentation allows the system to maintain error correction capability while freeing up bits for other purposes such as increased CRC detection, thereby improving both reliability and adaptability.
Solution Approach 2:
The patent recovers bits for reuse by discarding the correction of non-essential bits. The 2 bits that would traditionally be used for correcting non-critical errors are instead made available for other purposes like enhanced error detection, thus recovering resources without sacrificing essential error correction functionality.
3Reliability
If all 4 bits are corrected when an IO line fails, then complete error correction is provided, but system complexity and resource consumption increase
Solution Approach 1:
The patent applies partial action by implementing a simplified correction process that only addresses the 2 essential bits instead of all 4 bits. This reduces the complexity of the correction logic and decreases resource consumption while providing sufficient error correction for system reliability.
Solution Approach 2:
The patent segments the correction process into essential and non-essential parts, allowing the system to focus computational resources only on the critical 2 bits that need correction. This segmentation simplifies the overall correction process and reduces device complexity.
Data Source
AI summary
Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.