Memory I/O Bias Control During Microcontroller Low-Power Mode
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Solution Overview
Problem
Microcontrollers face issues with unintended memory input/output activation and deactivation due to floating states during low-power mode, leading to potential data loss and increased energy consumption.
Innovation Solution
Implementing a control unit with two power supply domains: one for active mode and one for low-power mode, using separate configuration means to maintain a stable logic state on memory inputs, employing existing pull-up and pull-down resistors within the microcontroller's I/O ports to ensure consistent biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the microcontroller enters low-power mode to reduce energy consumption, then power consumption is reduced, but the configuration means are reset and memory input/output pins become floating causing unintended activation
Solution Approach 1:
The patent divides the configuration system into two separate domains: first configuration means located in the first power supply domain that are reset in low-power mode, and second configuration means located in the second power supply domain that remain active. This segmentation allows the system to maintain reliable memory I/O configuration during low-power mode while still achieving power savings for the main configuration means.
Solution Approach 2:
The second configuration means in the second power supply domain acts as an intermediary that takes over the configuration function when the first configuration means are reset. This intermediary ensures continuous reliable configuration of memory I/O pins even when the primary configuration means is inactive, preventing floating states and unintended activations.
2Use of energy by moving object
If configuration means are reset in low-power mode to save energy, then power consumption is reduced, but leakage currents increase due to floating input/output pins
Solution Approach 1:
By segmenting the power supply domains and configuration means, the patent ensures that while the first configuration means are reset to save power, the second configuration means remain active to maintain proper biasing of memory I/O pins, thereby preventing leakage currents that would otherwise occur with floating pins.
Solution Approach 2:
The second configuration means serves as an intermediary that maintains proper electrical states on memory I/O pins during low-power mode, preventing floating conditions that would cause leakage currents and energy loss.
3Reliability
If separate configuration means are used for active and low-power modes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the configuration means into two separate domains with different power supply characteristics. This segmentation, while increasing structural complexity, ensures that memory I/O configuration remains reliable during mode transitions and in low-power operation, as the second configuration means takes over when the first is reset.
Data Source
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AI summary
According to one aspect, a system (SYS) is proposed comprising a control unit (CU) configured to be electrically connected to an input (IN) of a memory (MEM) via a communication interface (COM), the control unit (CU) having a first power supply domain (VCore) configured to be powered when the control unit (CU) is in an operating mode and a second power supply domain (VIO) configured to be powered when the control unit (CU) is in the operating mode and in the reduced power consumption mode, wherein the control unit (CU) has respectively in the first power supply domain (VCore) and in the second power supply domain (VIO) first configuration means and second configuration means adapted to configure a bias value of said input (IN) of the memory (MEM) via the communication interface (COM).