Memory I/O Circuit Substrate Biasing for Power-Speed Switching

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in reducing power consumption while maintaining operational efficiency, particularly in nonvolatile memory applications.

Innovation Solution

The implementation of a substrate bias voltage supply circuit that controls the application of different voltage levels to transistors within the input and output circuit, allowing for adjustable operating threshold voltages to optimize power consumption based on operational needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a fixed voltage level is applied to transistors in the input and output circuit, then the circuit operates at a constant speed, but power consumption cannot be reduced

Engineering Contradiction:
Improvepower consumptionVSAvoidoperational speed adjustment
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the substrate bias voltage adjustable rather than fixed. The substrate bias voltage supply circuit can dynamically change the voltage level applied to the substrate of transistors in the input and output circuit, enabling the operational characteristics to be adapted based on power consumption requirements while maintaining functional performance

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the electrical parameter (substrate bias voltage) of the transistors to control their operating threshold voltages. By adjusting the substrate bias voltage, the threshold voltage of transistors changes, which directly affects both power consumption and switching speed, allowing optimization of the trade-off between these two parameters

Inventive Principle:
Principle #35Parameter changes

2Speed

If the operating threshold voltage of transistors is reduced to increase speed, then high-speed operation is achieved, but power consumption increases

Engineering Contradiction:
Improveoperational speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent utilizes parameter changes by adjusting the substrate bias voltage to control the threshold voltage of transistors. When high-speed operation is needed, the substrate bias voltage is adjusted to reduce the threshold voltage, enabling faster switching. When power saving is prioritized, the substrate bias voltage is adjusted to increase the threshold voltage, reducing leakage current and power consumption

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system dynamically adjusts the substrate bias voltage based on operational requirements, allowing the transistor threshold voltages to be optimized in real-time. This dynamic control enables the circuit to switch between high-speed mode and low-power mode by changing the electrical characteristics of the transistors through substrate biasing

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reduced power consumption without significantly compromising speed, with a considerable reduction in current consumption, achieving a semiconductor memory device capable of reducing power consumption by approximately 16 mA per high-side transistor, and allowing for high-speed or low-speed operations based on user requirements.

Implementation Method 1

a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors

Methodology Applied
Scientific EffectSubstrate bias voltage effect:

Data Source

PatentUS20260080951A1Semiconductor memory device
Publication Date: 2026.03.19 KIOXIA CORP
  • US20260080951A1 patent drawing
  • US20260080951A1 patent drawing
  • US20260080951A1 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes an input and output pad group, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad group and the memory cell array. The input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.