Memory IO Margining with Dynamic Timing and Voltage Offsets

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Solution Overview

Problem

As communication speeds in memory subsystems increase, smaller timing margins make systems susceptible to variations in voltage and temperature, leading to bit errors and system instability, with existing methods risking data corruption during dynamic workload adjustments.

Innovation Solution

A memory subsystem with a reserved memory space for margining traffic, allowing dynamic monitoring and adjustment of IO settings through a rank bit, enabling continuous monitoring and tuning of TX/RX eye margins without disrupting normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If timing and voltage settings are modified during functional traffic to maintain TX/RX eye margins, then system reliability improves, but data corruption risk increases

Engineering Contradiction:
ImproveTX/RX eye margin stabilityVSAvoiddata corruption risk
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments memory traffic into functional traffic and margining traffic, allowing them to be handled separately. A rank bit is used to distinguish between these two types of traffic, enabling the system to perform margining operations on dedicated memory ranks without interfering with functional operations on other ranks. This segmentation resolves the contradiction by isolating the harmful margining operations from functional data paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces margining traffic as an intermediary mechanism. Instead of directly modifying timing and voltage settings during functional traffic (which causes data corruption), the system uses separate margining traffic to probe and measure eye margins. The results from this intermediary margining process then inform safe adjustments to the actual functional settings.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If memory controller stalls to measure and adjust margining settings, then measurement accuracy improves, but productivity decreases

Engineering Contradiction:
Improvemargining measurement accuracyVSAvoidsystem operational throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent enables continuous margining operations by allowing margining traffic to flow simultaneously with functional traffic through different memory ranks. Instead of stalling the memory controller to perform measurements, the system continuously sends margining traffic to probe eye margins while functional traffic continues uninterrupted. This maintains both measurement precision and system productivity through parallel continuous operations.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary margining measurements using dedicated margining traffic before making any actual timing or voltage adjustments to functional settings. This preliminary action allows the system to accurately determine the current eye margins and calculate safe adjustment parameters without interrupting functional operations, thus maintaining both measurement accuracy and continuous productivity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If communication speed increases to improve productivity, then data transfer rate improves, but timing margins decrease making system more susceptible to errors

Engineering Contradiction:
Improvecommunication speedVSAvoidtiming margin stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements continuous feedback monitoring of TX and RX eye margins through dedicated margining traffic. At increased communication speeds, the system continuously measures the actual eye margins using margining operations and uses this feedback to dynamically adjust timing and voltage settings. This feedback loop allows the system to maintain reliability at high speeds by automatically compensating for reduced timing margins through real-time parameter optimization.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4672006A1Dynamically insert timing and voltage offset control (VOC) offsets in input/output (IO) during functional traffic
Publication Date: 2025.12.31 INTEL CORP
  • EP4672006A1 patent drawingFigure 1
  • EP4672006A1 patent drawingFigure 2
  • EP4672006A1 patent drawingFigure 3

AI summary

A memory subsystem includes a memory space reserved for margining traffic. The memory controller sets a rank bit to select the reserved memory space and configures a physical interface with different settings to test. Thus, the system can have operational IO (input/output) settings and margining IO settings that can both be used at runtime. If the margining IO settings provide an improved error rate over the operational IO settings, the memory controller can reconfigure the operation IO settings.