Memory I/O Circuit With Flag-Based Error Blocking at High Data Rates
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Solution Overview
Problem
The increased speed of data input and output in semiconductor devices, such as DDR2, DDR3, and DDR4, leads to higher probabilities of errors during data transmission.
Innovation Solution
A semiconductor device with a memory circuit comprising multiple mats and a meta region, utilizing computational operations on addresses to generate column signals and flag signals to block or repair data outputs, and a data input and output circuit to generate data based on shifting signals, enhancing error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data input and output speed is increased, then productivity is improved, but reliability deteriorates due to higher error probability
Solution Approach 1:
The patent applies preliminary action by generating flag signals through computational operations on addresses before data transmission occurs. These flag signals predict potential error locations in advance, allowing the system to prepare correction mechanisms proactively rather than reactively after errors occur during high-speed data transmission.
Solution Approach 2:
The patent implements feedback by using the generated flag signals to control data output and transmission processes. The flag signals provide continuous feedback about potential error conditions, enabling the system to adjust its operation dynamically to maintain reliability even at increased data speeds.
2Reliability
If computational operations are performed on addresses to generate flag signals, then reliability is improved through error detection, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the address space into multiple segments and performing computational operations on each segment to generate corresponding flag signals. This approach breaks down the complex task of error detection across the entire address space into manageable smaller operations, reducing overall circuit complexity while maintaining comprehensive error detection capability.
Solution Approach 2:
The patent implements local quality by generating flag signals that are specific to particular address regions or segments rather than applying a uniform complex operation across all addresses. Each computational operation is tailored to the specific characteristics of its address segment, optimizing the balance between error detection reliability and circuit complexity for each local region.
Data Source
AI summary
A semiconductor device includes a memory circuit including a plurality of mats and a meta region and configured to block output of first internal data stored in the plurality of mats based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address during normal mode and configured to output second internal data from the meta region and a data input and output circuit configured to generate a plurality of data from the first internal data and the second internal data based on a plurality of shifting signals.