Memory I/O Impedance Calibration Across Read and Command Modes
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Solution Overview
Problem
As semiconductor memory devices increase in operating speed, signal transmission between the device and a memory controller experiences issues with swing width and distortion due to impedance mismatch, which are exacerbated by process, voltage, and temperature fluctuations.
Innovation Solution
A memory device with an impedance calibration circuit that divides the total impedance calibration section into multiple sub-impedance calibration sections, performing specific sub-impedance calibrations for different operational modes such as read, non-target read/write, and command operations, using external resistors to maintain consistent termination impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of the semiconductor memory device is increased, then the reading and writing speeds are improved, but signal distortion due to impedance mismatch becomes more problematic
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the termination impedance of the input-output circuit based on detected impedance conditions. The impedance calibration circuit modifies impedance parameters (resistance values) to match the characteristic impedance of external cables, thereby reducing signal reflection and distortion at high operating speeds. This is achieved through programmable termination resistors that can be configured to different impedance values.
2Device complexity
If a single impedance calibration is performed for the entire impedance calibration section, then the calibration process is simplified, but it cannot accommodate different impedance modes (read, non-target read/write, command)
Solution Approach 1:
The patent applies segmentation by dividing the single impedance calibration section into multiple sub-impedance calibration sections, each dedicated to a specific impedance mode (read mode, non-target read/write mode, and command mode). This allows independent calibration for each mode, enabling the system to adapt to different impedance requirements while maintaining manageable complexity through modular calibration processes.
Solution Approach 2:
The patent implements dynamics by making the termination impedance adjustable and reconfigurable based on the current operating mode. The impedance calibration circuit can dynamically switch between different calibration sections and apply appropriate termination values for read operations, write operations, and command transmissions, thereby adapting to varying impedance requirements in real-time.
Data Source
AI summary
Disclosed is a memory device, which comprises a memory cell array that includes a plurality of memory cells; an input/output circuit configured to transmit data received from an outside (e.g., an external source) through a data pad to the memory cell array or transmit data read from the memory cell array to the external source; and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input/output circuit. The impedance calibration circuit is further configured to divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.