Memory I/O Interface Circuit Sequential Power Switching
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Solution Overview
Problem
Existing memory devices face challenges in achieving high-speed I/O interface operations while maintaining low standby current, which is crucial for battery-operated systems and preventing issues like power droop and timing margin deterioration due to unpredictable shoot-through currents and charging/discharging currents.
Innovation Solution
The implementation of high-speed interface circuits that utilize power switch transistors to activate and deactivate high-speed circuit blocks in a sequential order, avoiding the need for tightly controlled delay circuits and minimizing shoot-through currents by using switch control circuits to manage power supply connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed interface circuits are used to achieve high-speed I/O operations, then the speed of read/write operations is improved, but standby current consumption increases due to shoot-through currents and charging/discharging currents
Solution Approach 1:
The patent applies preliminary action by using switch control circuits to pre-activate power switch transistors in a predetermined sequence before the high-speed circuit blocks are fully enabled. This sequential activation ensures that previous circuit blocks are completely deactivated before new ones are activated, preventing shoot-through currents and reducing standby current consumption while maintaining high-speed I/O operation capability
2Use of energy by moving object
If power switch transistors are used to control circuit activation, then standby current is reduced, but circuit complexity increases due to additional switch control circuits
Solution Approach 1:
The patent segments the high-speed interface circuit into multiple independent circuit blocks (first circuit block, second circuit block, etc.), each with its own power switch transistor and switch control circuit. This segmentation allows independent control of each block's power supply, enabling precise management of standby current while distributing the control complexity across multiple manageable units rather than requiring a single complex control system
Data Source
AI summary
An input/output interface circuit is provided for a memory device. The input/output interface circuit receives a first control signal and a second control signal, and provides an output clock signal. The input/output interface circuit includes a plurality of circuit blocks coupled in series, the a plurality of circuit blocks including an input terminal coupled to the first control signal and the second control signal, and an output terminal providing the output clock signal, a plurality of power switch transistors, each power switch transistor including a control terminal and coupled between a corresponding one of the circuit blocks and a power supply terminal, and a plurality of switch control circuits, each switch control circuit coupled to the control terminal of a corresponding one of the power switch transistors. The switch control circuits are configured to activate the circuit blocks in a first predetermined order and deactivate the circuit blocks in a second predetermined order.