Memory I/O Interface Using Least Significant Bit for Data Sequence Selection
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Solution Overview
Problem
Conventional memory devices with serial protocol interfaces require different devices to handle various data input or output sequences, leading to inefficiencies due to the unused least significant bit in double transfer rate or double data rate interfaces, which limits flexibility in data transfer.
Innovation Solution
A memory device with an I/O interface that can receive and output signals within a clock cycle or at a rising or falling edge, using a least significant bit to specify the data sequence, allowing for flexible and selectable output or input sequences, such as high-byte-first or low-byte-first, thereby optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a double transfer rate (DTR) or double data rate (DDR) interface is used with 8-bit bus width, then data transfer speed is improved, but the least significant bit (A0) becomes unused and data sequence flexibility is lost
Solution Approach 1:
The patent changes the function of the least significant bit (A0) from an address bit to a data sequence selection bit. By repurposing this previously unused parameter, the system can select between different data output sequences (normal, reverse, high-byte-first, low-byte-first) while maintaining the high-speed DTR/DDR interface operation.
Solution Approach 2:
The least significant bit is given multiple functions: it can be used for address selection in traditional modes and for data sequence selection in DTR/DDR modes. This multi-functionality allows a single memory device to serve multiple protocols and data sequence requirements without needing separate devices.
2Adaptability or versatility
If different data input or output sequences are required, then adaptability is improved, but device complexity increases as multiple devices are needed
Solution Approach 1:
The memory device incorporates multiple data sequence output capabilities (normal, reverse, high-byte-first, low-byte-first) within a single device. The least significant bit controls which sequence is active, allowing one device to replace what would traditionally require multiple specialized devices for different sequence requirements.
Solution Approach 2:
The data output sequence is made dynamically selectable during operation through the least significant bit control signal. This allows the system to switch between different data sequences on-the-fly without changing physical device connections or configuration, providing flexible adaptability.
3Measurement precision
If the least significant bit is used for address selection, then addressing precision is improved, but data transfer flexibility deteriorates in DTR/DDR mode
Solution Approach 1:
The patent changes the role of the least significant bit based on the operating mode. In traditional SDR modes, A0 functions as an address bit for precise memory location selection. In DTR/DDR modes, A0 is repurposed as a data sequence selection bit, controlling the output byte order while addressing is handled by higher-order bits.
Data Source
AI summary
A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.