Memory I/O Offset Logic for High-Speed Data Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current high-speed DRAM and SDRAM applications, particularly in graphics memory like GDDR5, face issues with smaller signal amplitudes and data valid windows due to narrower memory interfaces and reduced chip sizes, leading to unreliable data communication caused by small voltage biases in I/O interfaces.
Innovation Solution
The implementation of a memory system with a training circuit that determines transition thresholds for receiver sample circuits, adjusting signal levels using offset values to compensate for voltage biases, and employing decision feedback equalization to improve data detection accuracy across high-speed I/O buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high I/O speeds are implemented in DRAM applications, then bandwidth and data transmission rate are improved, but signal amplitude and data valid windows become smaller leading to unreliable communication
Solution Approach 1:
The patent applies preliminary action by performing interface training before normal data transmission. During this training phase, the system proactively determines transition thresholds and voltage biases for each sample circuit, and pre-calculates offset values that will be used during actual operation. This advance preparation ensures that when high-speed transmission begins, the receiver is already optimized to handle the reduced signal amplitudes and smaller data valid windows, thereby maintaining reliability at high speeds.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the transition thresholds for each sample circuit based on measured voltage biases. Instead of using fixed thresholds, the system modifies these parameters during interface training to compensate for process variations and voltage biases. This adaptive parameter adjustment allows the receiver to accurately detect data signals even when signal amplitudes are reduced due to high-speed operation, thus resolving the contradiction between speed and reliability.
2Area of stationary object
If narrower memory interfaces and reduced chip sizes are used, then device footprint is reduced, but signal amplitude and data valid windows decrease causing communication issues
Solution Approach 1:
The patent applies local quality by implementing individualized transition thresholds and offset values for each sample circuit rather than using uniform settings across all circuits. This per-circuit optimization accounts for local variations in voltage biases and signal characteristics that arise from the narrower memory interface and reduced chip size. By tailoring the detection parameters to each specific sample circuit's local conditions, the system maintains reliable communication despite the physical constraints of smaller chip dimensions.
3Ease of manufacture
If voltage biases in I/O interface are present, then manufacturing simplicity is maintained, but data detection accuracy deteriorates
Solution Approach 1:
The patent implements feedback by measuring the actual transition thresholds of each sample circuit during interface training and using these measurements to calculate appropriate offset values. The system creates a feedback loop where detection performance information is fed back into the system to adjust the sampling timing and thresholds. This feedback mechanism compensates for voltage biases without requiring complex manufacturing processes, as the biases are corrected through software-based calibration rather than hardware modification.
Data Source
AI summary
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.