Nonvolatile Memory I/O Pad Layout for High-Bandwidth Data Transfer
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Solution Overview
Problem
Current non-volatile memory devices face challenges in accommodating high bandwidth data input/output requirements due to limitations in the design of input/output pads, making it difficult to achieve high-speed data transfer.
Innovation Solution
The non-volatile memory device is designed with separate data pad sets and data path circuits for different memory areas on opposite sides of the chip, minimizing data path lengths and enabling high-bandwidth input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single set of input/output pads is used on one side of the flash memory chip, then the device structure is simple, but it is difficult to accommodate high bandwidth data input/output requirements
Solution Approach 1:
The patent divides the single set of input/output pads into multiple separate pad sets (first data pad set and second data pad set) disposed on different side surfaces of the cell array. Each pad set is electrically connected to different page buffer circuits, enabling parallel data input/output operations that increase bandwidth while distributing the structural complexity across multiple independent components.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement where all pads are on one side to a three-dimensional utilization by placing pad sets on different side surfaces of the cell array. This spatial distribution across multiple surfaces increases the effective I/O capacity without proportionally increasing the footprint area.
2Productivity
If multiple separate data pad sets are disposed on different side surfaces, then high bandwidth data input/output is achieved, but the data path circuit complexity increases
Solution Approach 1:
The data path circuit is segmented into multiple independent paths, with each path connecting a specific data pad set to its corresponding page buffer circuit. This segmentation allows each data path to operate independently, simplifying the control logic for each path while collectively achieving high bandwidth through parallel operation of multiple paths.
Solution Approach 2:
Each data path circuit is designed to handle both data input and data output operations for its associated page buffer circuit, making the data path circuits multi-functional. This universality reduces the need for separate dedicated input and output paths, thereby managing complexity while maintaining high bandwidth capability.
3Speed
If data pad sets are electrically separated for different memory areas, then high-speed data transfer is enabled, but the manufacturing process becomes more complex
Solution Approach 1:
The electrical separation of data pad sets is achieved through segmented wiring arrangements where each pad set has its own dedicated connection path to the cell array and page buffer circuits. This segmentation enables independent optimization of each data path for high-speed operation while using standardized manufacturing techniques for each segment, making the overall complex structure manufacturable through modular fabrication processes.
Data Source
AI summary
A non-volatile memory device includes a cell array having a first memory area and a second memory area, a first page buffer circuit configured to write first data into the first memory area or sense the first data stored in the first memory area, a second page buffer circuit configured to write second data into the second memory area or sense the second data stored in the second memory area, a first data pad set disposed on a first side surface of the cell array and electrically connected to the first page buffer circuit, and a second data pad set disposed on a second side surface of the cell array and electrically connected to the second page buffer circuit. The first data pad set and the second data pad set are electrically separated from each other.