Semiconductor Memory I/O Switch Reset Selection Unit
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Solution Overview
Problem
In semiconductor memory apparatuses, existing technologies consume unnecessary power due to reset signals being supplied to all I/O switches regardless of operational regions, leading to current consumption and inefficient power usage.
Innovation Solution
A semiconductor memory apparatus with a reset selection unit that selectively outputs reset signals to I/O switches based on mode signals and addresses, allowing only the necessary I/O switches in the selected unit cell regions to perform a reset operation, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reset signals are supplied to all I/O switches, then all I/O switches can be prepared for reading or writing operations, but unnecessary power is consumed by I/O switches in non-operational regions
Solution Approach 1:
The patent segments the I/O switches into multiple groups based on their connection to different bit line groups. A reset signal generation circuit generates separate reset signals for each group, allowing selective activation of only those I/O switches connected to currently accessed bit lines, thereby eliminating unnecessary power consumption in non-operational regions while ensuring operational readiness where needed
2Productivity
If reset signals are supplied to all I/O switches, then pre-charge operation can be performed across the entire array, but current consumption increases due to unnecessary switching operations
Solution Approach 1:
The patent applies local quality by generating reset signals selectively for specific I/O switch groups based on current access patterns. Instead of uniformly activating all switches, the system identifies which bit line groups are currently accessed and generates reset signals only for corresponding I/O switch groups, reducing unnecessary current consumption while maintaining adequate pre-charge operation coverage for active regions
Data Source
AI summary
A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in the column direction, I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks and a reset selection unit that selectively outputs a reset signal to each line of the I/O switches.