Memory I/O Circuit With Switched Drive and Termination Resistance
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Solution Overview
Problem
Existing memory technologies face challenges in impedance matching during different operations, leading to signal reflection and degradation, which affects data transmission quality and increases bit error rates.
Innovation Solution
A data input/output circuit with a parallel-to-serial conversion circuit, read enable signal generation circuit, and resistance control circuit that synchronizes impedance matching with read/write operations by using termination and output drive resistance control codes based on a read enable signal, allowing for multiplexed timing of resistance state switching and data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ODT resistance and output drive resistance are configured separately for different operations, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent combines the ODT resistance control and output drive resistance control into a single resistance control circuit. The circuit receives both termination resistance control code and output drive resistance control code, and uses a read enable signal to selectively output one of the two resistance control codes, thereby merging two separate control functions into one unified circuit structure.
Solution Approach 2:
The resistance control circuit is designed to perform multiple functions: it can output either termination resistance control code or output drive resistance control code based on the read enable signal state. This multi-functional design allows a single circuit to replace what would traditionally require separate control circuits for different operations.
2Loss of time
If separate control circuits are used for ODT and output drive resistance, then timing control is improved, but circuit area increases
Solution Approach 1:
The patent merges the control logic for ODT resistance and output drive resistance into a single resistance control circuit. By using a read enable signal to selectively enable different resistance control codes, the circuit maintains precise timing control while occupying less area than separate control circuits would require.
3Object-generated harmful factors
If impedance matching is not synchronized with data output timing, then signal reflection increases, but control simplicity is reduced
Solution Approach 1:
The resistance control circuit is configured to output the appropriate resistance control code in advance of data transmission. By using the read enable signal to proactively set the resistance state before data is output, the circuit ensures impedance matching is established prior to signal transmission, preventing signal reflection.
Solution Approach 2:
The circuit uses the read enable signal as a control input that automatically triggers the appropriate resistance configuration. This feedback mechanism ensures that the resistance state is dynamically adjusted based on the operational state, maintaining proper impedance matching without requiring complex external control logic.
Data Source
AI summary
Embodiments of this application provide a data input/output circuit and a memory. The circuit comprises: a parallel-to-serial conversion circuit to receive N data pieces and serially output them in a first time period; a read enable signal generation circuit to generate a read enable signal active during the first time period; a resistance control circuit to receive termination and output drive resistance control codes and the read enable signal, and to select which code to output based on the read enable signal; and an output drive circuit to receive the N data pieces and the selected code, and to either configure an output drive resistance to output the data or configure a termination resistance, where N is a positive integer greater than 1.