Semiconductor Memory IO Terminal Sequence Switching
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing the sequence of IO terminals, particularly in NAND flash memory systems, where the sequence of IO terminals between the controller chip and the memory chip must match for proper data delivery, leading to complexities in design and increased costs, especially in three-dimensional non-volatile memory configurations.
Innovation Solution
The implementation of an IO switch unit within the semiconductor device that can dynamically switch the sequence of IO lines connected between the IO terminals and the memory cell array, allowing for flexible sequencing based on control signals, enabling seamless data transfer regardless of the terminal sequence between the controller and memory chips, including both two-dimensional and three-dimensional configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sequence of IO terminals is fixed to match between controller chip and memory chip, then proper data delivery is achieved, but design complexity increases and multiple controller chip variants are required
Solution Approach 1:
The patent implements a dynamic IO terminal sequence switching mechanism that allows the controller chip to adaptively change the connection sequence between IO terminals and IO lines based on the memory chip configuration. This dynamic switching capability eliminates the need for multiple fixed-sequence controller chip variants while ensuring correct data delivery, directly resolving the technical contradiction between reliability and device complexity.
2Reliability
If multiple controller chip variants are used to match different memory chip configurations, then proper data delivery is ensured, but manufacturing cost increases
Solution Approach 1:
The patent makes the controller chip universal by incorporating an IO terminal sequence switching unit that can adapt to different memory chip configurations (2D, 3D, different IO terminal sequences). This single universal controller chip design eliminates the need to manufacture multiple variants, directly reducing manufacturing costs while maintaining reliable data delivery across all configurations.
3Ease of manufacture
If IO terminal sequence is fixed in design, then manufacturing is simpler, but adaptability to different memory configurations is reduced
Solution Approach 1:
The patent introduces a dynamic switching mechanism that allows the controller chip to adapt its IO terminal sequence to match different memory chip configurations (2D, 3D, various IO terminal arrangements). This dynamic adaptability is achieved through control signals that reconfigure the connection sequence, maintaining design simplicity while enabling broad configuration compatibility.
Data Source
AI summary
According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.