Memory I/O Skew Tuning to Eliminate Frequency Holes
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Solution Overview
Problem
Conventional computing devices face issues with phase jitter between data and clock signals, leading to memory operating frequency holes, which can result in lower device performance or errors, and existing solutions like wide band isolation or over/under clocking are costly or impractical.
Innovation Solution
The method involves setting the skew between the data signal path and the clock signal path away from the spectral peak of a phase jitter transfer function, using variable delay elements to attenuate transmit noise and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide band isolation is imposed through silicon design or package design to address phase jitter, then phase jitter is reduced, but cost increases
Solution Approach 1:
The patent changes the timing parameter (skew) between data and clock signals to operate away from spectral peaks of the phase jitter transfer function. By adjusting the skew parameter to align with spectral nulls, the system reduces phase jitter effects without requiring costly wide band isolation structures in silicon or package design.
2Reliability
If over or under clocking is applied to address phase jitter, then signal timing is adjusted, but practicality decreases
Solution Approach 1:
Instead of changing clock frequency (over/under clocking), the patent changes the skew parameter between data and clock signals. This approach maintains practical operability while achieving proper signal timing by positioning the operating point away from spectral peaks of the phase jitter transfer function.
3Reliability
If skew between data signal path and clock signal path is not properly managed, then phase jitter causes errors, but device performance decreases
Solution Approach 1:
The patent employs a feedback mechanism where the system measures or characterizes the phase jitter transfer function, identifies spectral peaks, and adjusts the skew parameter accordingly. This closed-loop approach ensures errors are reduced while maintaining optimal device performance by continuously positioning the operating point away from problematic frequency regions.
Solution Approach 2:
The system dynamically adjusts the skew parameter based on the identified spectral characteristics of the phase jitter transfer function. By changing the skew parameter to align with spectral nulls rather than peaks, the system simultaneously reduces errors and maintains high device performance.
Data Source
AI summary
Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.