Memory I/O Training Circuitry Address Selection
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Solution Overview
Problem
Current DRAM initialization methods often result in system hangs due to zero margin errors caused by failing memory rows, leading to unnecessary channel disabling and reduced memory reliability, especially during cold reboots.
Innovation Solution
The implementation of a memory I/O training circuitry that dynamically selects and avoids failing memory addresses during write DQ delay training, using a post-package repair list to identify and replace faulty rows, thereby preventing zero margin errors and enhancing memory reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory initialization uses fixed address training methods, then the initialization process is simple, but zero margin errors occur due to failing memory rows causing system hangs
Solution Approach 1:
The patent applies preliminary action by performing memory training on multiple different starting addresses until a successful training is achieved. The system pre-determines a sequence of candidate starting addresses and systematically tries them in order before proceeding with normal memory operations. This preliminary address selection process prevents zero margin errors by ensuring that training does not begin on failing memory rows, thereby resolving the contradiction between reliability and complexity.
2Reliability
If memory training is performed on all addresses, then comprehensive coverage is achieved, but training time increases and system hangs occur due to failing rows
Solution Approach 1:
The patent applies segmentation by dividing the memory address space into multiple segments and performing training on a limited number of representative addresses within each segment rather than exhaustively training all addresses. The system selects specific starting addresses that represent different memory regions, performs training on these segmented samples, and proceeds without exhaustive coverage. This segmentation approach maintains reliability by sampling critical regions while significantly reducing training time by avoiding redundant training on all addresses.
3Adaptability or versatility
If failing memory rows are not avoided, then address selection is straightforward, but channel disabling occurs reducing memory availability
Solution Approach 1:
The patent applies dynamics by implementing a dynamic address selection mechanism that adapts the training starting address based on previous training results and memory characteristics. The system dynamically determines the next starting address from a predefined sequence based on whether previous training attempts succeeded or failed, rather than using a fixed address. This dynamic adaptation allows the system to avoid failing memory rows and maintain channel availability while managing address selection complexity through algorithmic determination rather than exhaustive searching.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed to select addresses for memory training. An example non-transitory computer readable medium comprising instructions that, when executed, cause a machine to determine a first memory address at which to perform memory input/output training based on an identification of a second memory address that is associated with an error, and cause the memory input/output training to be performed at the first memory address.