Semiconductor Memory Device Ion Implantation Current Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

2T N-type ETOX semiconductor memory cells face issues with increased current consumption during programming through CHEI and reduced operating speed and vulnerability to disturbance when using the BTBT Assisted Hot Hole Injection method.

Innovation Solution

The semiconductor memory device employs a configuration with specific ion implantation regions and gate insulation layers to enable precise control of current during programming through BTBT Assisted Hot Electron Injection and efficient erase operations via Hot Hole Injection, optimizing the structure for improved program speed and minimal disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If CHEI method is used for programming, then programming capability is achieved, but current consumption is increased

Engineering Contradiction:

Improvecurrent consumptionVSAvoidprogramming capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the programming mechanism from CHEI to BTBT-assisted HHI by modifying the voltage parameters applied to the select gate and control gate. This parameter change enables programming through band-to-band tunneling and hot hole injection, achieving programming capability while reducing current consumption to several tens of nA levels.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If BTBT Assisted Hot Hole Injection method is used for programming, then programming is achieved, but operating speed is deteriorated and vulnerability to disturbance increases

Engineering Contradiction:

Improveprogramming capabilityVSAvoidoperating speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent segments the gate structure into multiple independent gates (first select gate, second select gate, and control gate) with separate voltage control. This segmentation enables precise control of the band-to-band tunneling and hot hole injection processes, achieving fast programming speeds while maintaining reliability and reducing disturbance vulnerability through independent gate voltage optimization.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for accurate current control during programming and rapid erase operations, minimizing disturbance and maintaining threshold voltage stability, with program speeds of 5 μsec to 20 μsec and precise control of several tens of nA current levels.

Implementation Method 1

programmed through a Band-to-Band-Tunneling (BTBT) Assisted Hot Hole Injection method

Methodology Applied

Scientific EffectBand-to-Band Tunneling:

Implementation Method 2

programmed through a Channel Hot Electron Injection (CHEI) method

Methodology Applied

Scientific EffectHot Electron Injection:

Implementation Method 3

accurately and promptly controlling an erase operation by the minimum bit cell unit through a Hot Hole Injection (HHI) method

Methodology Applied

Scientific EffectHot Hole Injection:

Implementation Method 4

forming a first ion implantation region in the semiconductor substrate between the select gate and the floating gate

Methodology Applied

Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS8446763B2Semiconductor memory device, method of manufacturing the same, and cell array of semiconductor memory device

Publication Date: 2013.05.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor memory device, a method of manufacturing the same, and a cell array of a semiconductor memory device are provided. The semiconductor memory device includes: a first gate insulation layer and a second gate insulation layer, being spaced a predetermined distance from each other, on a portion of a semiconductor substrate; a select gate on the first gate insulation layer; a floating gate on the second gate insulation layer; a third gate insulation layer on the floating gate; a control gate on the third gate insulation layer; a first ion implantation region in the semiconductor substrate between the select gate and the floating gate; a second ion implantation region in the semiconductor substrate at a side of the select gate opposite the first ion implantation region; and a third ion implantation region in the semiconductor substrate at a side of the floating gate opposite the first ion implantation region.