Memory Circuit Isolation Structure for Bipolar Selector Integration
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Solution Overview
Problem
Existing electronic devices with memory circuits and logic circuits face challenges in optimizing the integration and isolation of memory elements and logic transistors, particularly in terms of depth and material compatibility, which affects performance and efficiency.
Innovation Solution
The integration of memory circuits with bipolar selector transistors and logic circuits with finned field-effect transistors is achieved through the use of isolation structures with spacers, where the memory and logic circuits share the same or different depths, and the use of phase-change materials for memory elements, all fabricated on a semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory circuits and logic circuits are integrated on the same semiconductor substrate, then device functionality and efficiency are improved, but isolation and depth compatibility between different circuit types become more difficult to achieve
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions: a first region for memory circuits and a second region for logic circuits. Each region has its own dedicated isolation structures (first isolation structures for memory, second isolation structures for logic), allowing independent optimization of isolation depth for each circuit type while maintaining integration on the same substrate.
Solution Approach 2:
The patent applies different isolation structures with different depths to different locations on the substrate. The first isolation structures extend to a first depth in the memory region, while the second isolation structures extend to a second depth in the logic region. This local differentiation allows each circuit type to have optimal isolation characteristics tailored to its specific requirements.
2Reliability
If different isolation depths are used for memory and logic circuits, then circuit performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation structures into two distinct types: first isolation structures for memory circuits and second isolation structures for logic circuits. Each type can have different depths and characteristics, allowing performance optimization for each circuit type without requiring a single complex isolation structure design.
Solution Approach 2:
Both first and second isolation structures use the same basic STI (shallow trench isolation) design and material composition, but differ in depth. This universal approach to isolation structure design simplifies manufacturing processes while still allowing depth differentiation to optimize performance for different circuit types.
3Adaptability or versatility
If bipolar selector transistors are used in memory elements, then memory operation capability is improved, but integration with finned field-effect transistors becomes more challenging
Solution Approach 1:
The patent separates bipolar selector transistors into memory cells located in the first region, while finned field-effect transistors are placed in the second region. This spatial segmentation allows each transistor type to be optimized for its specific function without compromising the other, facilitating integration of different transistor technologies on the same substrate.
Solution Approach 2:
The patent implements region-specific transistor designs: bipolar transistors in the memory region with characteristics optimized for memory operations, and finned field-effect transistors in the logic region with characteristics optimized for logic operations. This local quality approach allows diverse transistor types to coexist on the same substrate.
Data Source
Figure 1A~1B
Figure 1C~3b
Figure 4a~7A
AI summary
This description relates to an electronic device comprising: - a semiconductor substrate (13); - an insulating layer (18), on and in contact with the semiconductor substrate;and - a memory circuit comprising a plurality of memory cells, each comprising a bipolar selection transistor disposed in and on the semiconductor substrate, each bipolar selection transistor comprising a base region (29, 15), an emitter region (27) and a collector region (17), in which each bipolar selection transistor comprises an insulation structure (16) of a first dielectric material, the insulation structure comprising an upper part extending vertically in the insulating layer and a lower part extending vertically in the semiconductor substrate between the base region and the emitter region, the lateral faces of the upper part of the insulation structure being covered by spacers (21) of a second dielectric material.;