Memory Isolation for Single Bit Error Mitigation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current computer systems are unable to effectively reduce double bit memory faults without halting processing and rebooting, which is problematic for mission-critical applications that cannot be interrupted.

Innovation Solution

A method and system that isolate memory portions with single bit errors by reallocating and locking them to prevent further errors, allowing continuous operation without data corruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system halts and reboots after detecting a double bit error, then data corruption is prevented, but system availability and mission-critical application continuity deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidsystem availability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory space is segmented into multiple pages, and when a double bit error is detected in a specific page, only that particular page is isolated rather than halting the entire system. This selective segmentation allows the rest of the memory and running applications to continue operating normally, thus maintaining system availability while preventing data corruption in the affected area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating the faulty memory page differently from the rest of the memory. The faulty page is marked and isolated specifically, while other pages continue to function normally. This localized approach prevents the error from propagating system-wide, thereby maintaining overall system reliability and productivity.

Inventive Principle:
Principle #3Local quality

2Reliability

If the system isolates faulty memory pages continuously, then memory fault reduction is improved, but device complexity increases

Engineering Contradiction:
Improvememory fault reductionVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary action by continuously monitoring memory pages for double bit errors and pre-isolating faulty pages before they can cause data corruption. The memory management unit proactively identifies and marks faulty pages, preventing potential errors from affecting system operations. This advance preparation reduces memory faults while maintaining manageable complexity through automated monitoring and isolation mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7308603B2Method and system for reducing memory faults while running an operating system
Publication Date: 2007.12.11 GOOGLE LLC
  • US7308603B2 patent drawing
  • US7308603B2 patent drawing
  • US7308603B2 patent drawing

AI summary

Method and system for reducing memory faults for computer systems. In one aspect, a notification is received that indicates that a single bit error has been detected in a portion of memory of the computer system. A service program is used to isolate the portion of the memory that includes the detected single bit error by allocating the portion of memory to itself, such that the portion of memory may no longer be accessed for data reading or writing by programs running on the computer system.