Isolation Cells for Memory Area Reduction
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Solution Overview
Problem
Existing memory technologies have large memory cell sizes due to the size of isolation transistors, which increases the overall area of the memory circuit.
Innovation Solution
The introduction of first and second isolation cells with a similar structure to memory cells, but with a smaller size, where the doped regions and control gate structures are connected to serve as connection and control terminals, reducing the size while maintaining isolation functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation transistors are used to provide isolation functionality in memory circuits, then the isolation function is achieved, but the memory circuit area increases
Solution Approach 1:
The patent uses simplified isolation cells that copy the essential structure of memory cells (floating gate and control gate) but with reduced complexity. These isolation cells replicate the charge storage and control mechanisms needed for isolation functionality while removing unnecessary components, achieving the same isolation effect with smaller area.
Solution Approach 2:
The patent changes the structural parameters of the isolation elements by using only the critical components (floating gate and control gate) without the full memory cell structure. This parameter reduction maintains the electrical isolation function while significantly decreasing the area occupied by each isolation element.
2Reliability
If high voltage transistors are used for isolation, then isolation functionality is maintained, but the transistor size and overall memory size increase
Solution Approach 1:
The patent extracts only the essential isolation functionality from the complete transistor structure. By taking out the critical charge storage and control elements (floating gate and control gate) while removing the bulk transistor structure, the isolation function is preserved with minimal size.
Solution Approach 2:
The patent employs simplified isolation cells that are structurally simpler and smaller than full transistors. These reduced-structure isolation elements serve their purpose effectively but occupy minimal space, analogous to using a lightweight, purpose-specific component rather than a heavy-duty general-purpose component.
Data Source
AI summary
Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof.