Memory Address Isolation Mapping for Uniform Access Across Compute Dies
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Solution Overview
Problem
In server processing systems with dis-aggregated dies, high data access latencies and interconnect power consumption occur due to multiple data movements across the interconnect fabric and EMIB boundaries, leading to increased memory bandwidth and die-to-die interconnect bandwidth consumption.
Innovation Solution
Implementing a uniform memory access (UMA) architecture with isolation domains by mapping system memory physical addresses to quality of service (QoS) and security isolation domains, using address decoder tables to facilitate data communications and maintain consistent access latencies across compute dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dis-aggregated dies are used to increase core count, then processing capability is improved, but data access latency increases
Solution Approach 1:
The patent segments the memory address space into multiple isolation domains (e.g., domain 0, domain 1, domain 2) and maps different physical memory ranges to each domain. This segmentation allows each compute die to have dedicated memory regions, reducing the need to access remote memory through the interconnect fabric and thereby lowering data access latency while maintaining high processing capability through multi-core architecture.
Solution Approach 2:
The patent introduces an address decoder table as an intermediary component that translates memory access requests into isolation domain identifiers. This intermediary enables the system to efficiently route memory accesses to appropriate isolation domains without traversing the entire interconnect fabric, thus reducing latency while preserving the benefits of dis-aggregated die architecture.
2Quantity of substance
If multiple data movements across interconnect fabric are used to access memory, then memory bandwidth is improved, but interconnect power consumption increases
Solution Approach 1:
The patent assigns local memory regions to specific isolation domains, allowing compute dies to access their local memory directly without traversing the interconnect fabric. This local quality approach maintains high memory bandwidth for local accesses while significantly reducing interconnect traffic and power consumption for remote accesses.
Solution Approach 2:
By segmenting the address space into isolation domains with dedicated memory regions, the patent reduces the volume of data that needs to traverse the interconnect fabric. This segmentation enables efficient local memory accesses while preserving overall memory bandwidth capability, thereby reducing interconnect power consumption without sacrificing memory performance.
3Adaptability or versatility
If multiple data movements across EMIB boundaries are used, then memory access capability is improved, but die-to-die interconnect bandwidth consumption increases
Solution Approach 1:
The patent segments the memory address space into isolation domains and associates specific physical memory ranges with each domain. This segmentation enables compute dies to access their designated memory regions directly, reducing the need for data movements across EMIB boundaries and thereby lowering die-to-die interconnect bandwidth consumption while maintaining versatile memory access capability through the isolation domain mapping mechanism.
Solution Approach 2:
The address decoder table serves as an intermediary that translates memory addresses into isolation domain identifiers, enabling efficient memory access without requiring multiple data movements across EMIB boundaries. This intermediary approach maintains versatile memory access capability while reducing the bandwidth consumption on die-to-die interconnect.
4Reliability
If isolation domains are implemented for QoS and security, then access control is improved, but address mapping complexity increases
Solution Approach 1:
The patent introduces an address decoder table as an intermediary component that handles the complexity of address mapping to isolation domains. This intermediary absorbs the complexity of maintaining QoS and security isolation, presenting a simplified interface to the rest of the system while ensuring reliable access control through the isolation domain mapping mechanism.
Data Source
AI summary
Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input/output (I/O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.