Memory Isolation Stage for Power Reduction in Multi-Core Systems
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Solution Overview
Problem
In multi-core processor systems with multiple memories, existing technologies consume power even when memories are not being accessed, leading to inefficiencies in power management and increased energy consumption.
Innovation Solution
The implementation of isolation stages between memory controllers and memories, which isolate the memory from clock and data signals when not addressed, using flip-flops and gates to toggle and delay clock signals, allowing for selective activation of memories only when needed, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory ports remain active ready to respond to requests, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The memory system dynamically transitions between active and isolated states based on access requirements. When a memory is not being accessed, the isolation stage isolates it from the clock signal, transitioning the memory into a low-power state while maintaining the ability to quickly resume operation when needed.
Solution Approach 2:
The memory clock signal is provided periodically only when needed. The isolation stage gates the clock signal based on memory access requirements, providing clock cycles during active periods and stopping clock provision during inactive periods, thereby reducing overall power consumption while maintaining access performance when required.
2Use of energy by moving object
If isolation stages are added to isolate memory when not accessed, then power consumption is reduced, but device complexity increases
Solution Approach 1:
An isolation stage is introduced as an intermediary component between the memory controller and the memory. This isolation stage includes a clock gate that controls clock signal transmission and isolation logic that manages data bus isolation, enabling power reduction without requiring fundamental changes to the memory or controller architecture.
3Use of energy by moving object
If clock signal is blocked to isolate memory, then power consumption is reduced, but memory access timing may be affected
Solution Approach 1:
The isolation stage is designed to manage timing transitions proactively. Before isolating the memory, the system ensures all necessary data has been transferred. When isolation occurs, the timing of clock edges is carefully controlled to ensure that memory operations are complete, and when the memory is reactivated, the clock signal resumes with appropriate timing to maintain access performance.
Data Source
AI summary
Embodiments of a method and device are disclosed. In an embodiment, a controller includes a plurality of memories each having registers that are accessible using an address, a plurality of memory controllers each coupled to a memory and configured to control read and write operations to the respective coupled memory, a bus coupled to each of the memory controllers configured to communicate data and commands to each of the memory controllers, a plurality of processing cores coupled to the bus and configured to read and write data to the memories through the memory controllers, and a plurality of isolation stages, each isolation stage being coupled between a memory controller and a memory and configured to isolate the respective memory from receiving a memory clock signal when the memory is not addressed by the memory controller.