Nonvolatile Memory Fabrication via Isolation Trench Segmentation
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Solution Overview
Problem
The existing methods for fabricating nonvolatile memory devices face challenges such as pattern density differences between the cell and peripheral circuit regions, leading to variations in etching speeds, filling thickness, and CMP processes, which increase costs, time, and complexity, and result in the leaning phenomenon of conductive layers due to increased mask pattern formation steps.
Innovation Solution
A method is developed to separately form isolation trenches and gate patterns in the cell and peripheral circuit regions, allowing for uniform process execution by selectively etching layers and omitting additional mask pattern formation steps, thereby reducing the loading effect and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional mask pattern formation steps are performed to separately process cell and peripheral circuit regions, then manufacturing precision can be improved, but device complexity and process time increase
Solution Approach 1:
The substrate is divided into cell region and peripheral circuit region with different pattern densities. Isolation trenches are formed to physically separate these regions, allowing independent processing optimization for each region without requiring additional mask steps.
Solution Approach 2:
Different regions of the substrate are given different local structures: the cell region has high pattern density with closely spaced memory cells, while the peripheral circuit region has low pattern density with larger spaced circuits. This local differentiation allows each region to be processed according to its specific requirements.
2Ease of manufacture
If conventional fabrication methods are used with uniform processing across cell and peripheral circuit regions, then process simplicity is maintained, but manufacturing precision deteriorates due to loading effects
Solution Approach 1:
Isolation trenches are formed in advance before subsequent processing steps. This preliminary action creates physical separation between cell and peripheral circuit regions, preventing loading effects during etching and other processes, while maintaining overall process simplicity.
3Productivity
If isolation trenches are formed in both cell and peripheral circuit regions simultaneously, then process time is reduced, but manufacturing precision deteriorates due to pattern density differences
Solution Approach 1:
The substrate is segmented into cell and peripheral circuit regions with isolation trenches. This segmentation allows the two regions to be processed independently in subsequent steps, ensuring uniform filling thickness in each region despite different pattern densities.
Solution Approach 2:
Each region is given local processing attention: the cell region receives processing optimized for high pattern density, while the peripheral circuit region receives processing optimized for low pattern density, ensuring uniform results in each zone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniformity in the fabrication process, reduces process time, cost, and complexity, and prevents failures by decoupling the formation of isolation trenches and gate patterns, allowing for simultaneous ion implantation and eliminating the need for additional mask pattern formation.
Implementation Method 1
a first isolation trench in the cell region by selectively etching the first conductive layer, the first insulation layer, and the substrate of the cell region
Implementation Method 2
simultaneous ion implantation
Data Source
AI summary
A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.