Memory Isolation Units for Shared I/O Retention Mode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices with shared I/O circuits face signal delay and significant die area consumption due to level shifters, which are necessary to handle voltage differences between storage arrays operating in different domains, and struggle with isolating bitlines during retention mode to prevent interference.
Innovation Solution
Incorporating isolation units between each storage array and the shared I/O unit, connected through separate switched voltage domains via power gating circuits, allowing the isolation units to isolate bitlines from the I/O data paths when an array is in low-voltage or retention mode, thus eliminating the need for level shifters in the data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level shifters are used in the data path to handle voltage differences between storage arrays and shared I/O, then voltage compatibility is improved, but signal delay increases and die area increases
Solution Approach 1:
The patent extracts the level shifting function from the data path by introducing separate level shifters that are not in the critical signal path. The level shifters are placed in parallel with the bitline connections, allowing voltage conversion without adding delay to the critical path. This separates the voltage compatibility function from the signal transmission path.
Solution Approach 2:
The patent introduces isolation units as intermediary components between the storage arrays and the shared I/O circuit. These isolation units include level shifters and switches that mediate the interaction between different voltage domains, allowing voltage differences to be managed without direct coupling in the data path.
2Reliability
If level shifters are used in the data path to handle voltage differences, then voltage compatibility is improved, but die area increases
Solution Approach 1:
The patent segments the level shifting function by providing separate level shifters for each storage array connection rather than using a single shared level shifter circuit. This segmentation allows the level shifters to be positioned closer to the array outputs, reducing the overall area required for voltage conversion infrastructure.
Solution Approach 2:
The isolation units serve as intermediary components that consolidate the level shifting and isolation functions in a compact structure. By integrating the level shifters within the isolation units rather than placing them throughout the data path, the overall die area is reduced while maintaining voltage compatibility.
3Productivity
If storage arrays operate in different voltage domains to optimize performance, then operational efficiency is improved, but interference between arrays increases
Solution Approach 1:
The patent introduces isolation units as intermediary components between storage arrays operating in different voltage domains and the shared I/O circuit. These isolation units include level shifters and switches that mediate the interaction, allowing arrays to operate independently in different voltage domains while preventing interference through proper isolation and signal conditioning.
Solution Approach 2:
The patent extracts the isolation function from the shared I/O circuit by placing isolation units at the array interfaces. This extraction allows the shared I/O circuit to remain clean and free from voltage domain conflicts, while the isolation units handle the interference prevention at the point of connection to each array.
Data Source
AI summary
A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.