Nonvolatile Memory ISPP Bit Line Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory devices face challenges in optimizing program distribution across memory cells during incremental step pulse program (ISPP) operations, leading to inefficiencies in programming completion.
Innovation Solution
A nonvolatile memory device with a peripheral circuit and control logic circuit that performs program loops, including a setup operation and application of program pulses to selected word lines, with specific voltage level settings for bit lines to enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional incremental step pulse program (ISPP) operation is used, then the programming process is simple to implement, but the program distribution across memory cells is poor leading to incomplete programming
Solution Approach 1:
The patent divides the programming operation into multiple program loops, where each loop performs a setup operation followed by an application operation. The setup operation configures bit lines to specific voltage levels, and the application operation applies program pulses to selected word lines. This segmentation allows precise control over program distribution across memory cells while maintaining systematic implementation
Solution Approach 2:
The patent performs a setup operation before the application operation in each program loop. The setup operation pre-configures the bit lines to appropriate voltage levels based on the target program state, ensuring that when program pulses are applied, the memory cells receive the correct programming conditions. This preliminary action enables accurate program distribution without requiring complex real-time adjustments
2Manufacturing precision
If multiple program loops are performed with different voltage levels, then programming accuracy is improved, but the programming time increases
Solution Approach 1:
The patent implements periodic program loops that repeatedly perform setup and application operations with incrementally adjusted voltage levels. Each loop verifies programming status and adjusts subsequent voltage levels based on previous results, enabling systematic achievement of target program states while avoiding redundant operations through verification feedback
Solution Approach 2:
The patent incorporates verification operations within each program loop that check whether memory cells have reached the desired program state. Based on verification results, the control logic circuit adjusts the voltage levels for subsequent program pulses, ensuring programming accuracy is achieved with the minimum necessary number of loops, thereby optimizing programming time
3Manufacturing precision
If voltage levels are adjusted for different bit line groups, then program distribution is enhanced, but the control complexity increases
Solution Approach 1:
The patent applies different voltage levels to different groups of bit lines based on their specific programming requirements. The control logic circuit identifies which bit line groups need higher or lower voltage levels and configures them accordingly during the setup operation. This localized voltage control enhances program distribution accuracy without requiring complex global voltage adjustment mechanisms
Solution Approach 2:
The control logic circuit is designed to universally handle voltage level configuration for multiple bit line groups through a standardized setup operation procedure. The same control structure and voltage level selection mechanisms are reused across different program loops and bit line groups, reducing overall control complexity despite the differentiated voltage requirements
Data Source
AI summary
A nonvolatile memory device includes: a peripheral circuit for repeatedly performing program loops each including a program operation including a setup operation on the plurality of bit lines and an application operation of applying a program pulse to a selected word line and the verification operation, and a control logic circuit for controlling the peripheral circuit, wherein the peripheral circuit performs a first program loop of the program loops by: applying each a first and a second program pulses in each a first and a second section of the application operation, setting a first bit line to a first level and a second bit line to a second level lower than the first level from a start of the setup operation until an end of the first section, and resetting the first and the second bit line to the second level in the second section.