Memory Error Correction Using Iterative LDPC and RS Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in error correction due to the sequential processing of inner and outer error correction codes, leading to prolonged correction times and reduced reliability.
Innovation Solution
A memory system employing an iterative correction method that combines LDPC and RS codes, where a C1 code performs initial corrections, generates a syndrome for a set of C2 frames, and then performs a C2 correction using this syndrome, leveraging the linearity of the C2 code to update syndromes during the process, thereby simplifying error correction and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential error correction processing using C1 code and C2 code is performed, then error correction capability is improved, but correction time becomes long
Solution Approach 1:
The C1 error correction code is applied first to perform preliminary error correction on the read data before C2 correction. This preliminary action reduces the error burden on the subsequent C2 correction process, enabling faster overall correction while maintaining high reliability
Solution Approach 2:
The error correction process is segmented into two distinct stages: C1 correction processing and C2 correction processing. Each stage handles different aspects of error correction with optimized algorithms, allowing parallel processing paths and reducing total correction time while maintaining comprehensive error correction capability
2Reliability
If iterative correction is performed on multiple frames, then error correction capability is improved, but processing complexity increases
Solution Approach 1:
The syndrome calculation unit is designed to universally handle syndrome calculation for multiple C2 frames in a unified manner. The same syndrome calculation logic is applied iteratively across different frames and correction rounds, reducing the need for frame-specific processing logic and simplifying the overall system architecture
Solution Approach 2:
The iterative correction process nests multiple correction rounds within a unified control framework. Each iteration contains nested operations of syndrome calculation, error detection, and correction, with the outer loop managing frame-level coordination and the inner loops handling byte-level correction details, organizing complexity hierarchically
Data Source
AI summary
A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.