Semiconductor Memory Junction Barrier Layer Thickness Variation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing junction resistance and preventing outward diffusion of impurities, which leads to increased contact resistance and deterioration of transistor characteristics.
Innovation Solution
The implementation of a transistor with a junction structure that includes a barrier layer with varying thickness and silicon content, formed by a multilayer structure of metal silicide and silicon, to prevent impurity diffusion and reduce contact resistance, along with a contact pad that gap-fills a recess in the substrate, enhancing the reliability of semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional junction structure is used, then the device structure is simple, but the contact resistance increases and transistor characteristics deteriorate due to outward diffusion of impurities
Solution Approach 1:
The barrier layer is segmented into multiple layers with different thicknesses: a first barrier layer with greater thickness formed over the bottom surface of the recess, and a second barrier layer with lesser thickness formed over the side surface of the recess. This segmentation prevents outward diffusion of impurities from the junction while reducing contact resistance, thereby improving transistor characteristics without excessive complexity
Solution Approach 2:
Different regions of the barrier layer are given different local properties: the bottom surface region receives a thicker barrier layer to prevent impurity diffusion outward, while the side surface region receives a thinner barrier layer to reduce contact resistance. This local differentiation optimizes both protection and electrical performance
2Reliability
If the barrier layer thickness is increased to prevent impurity diffusion, then impurity diffusion is reduced, but contact resistance increases
Solution Approach 1:
The barrier layer is designed with non-uniform thickness distribution: thicker over the bottom surface to prevent impurity diffusion, and thinner over the side surface to reduce contact resistance. This local quality variation simultaneously achieves both objectives without compromise
Solution Approach 2:
The barrier layer is divided into functionally distinct segments: a first barrier layer for impurity diffusion prevention and a second barrier layer for contact resistance reduction. This segmentation allows each segment to optimize its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces contact resistance and prevents impurity diffusion, thereby improving the reliability and performance of semiconductor memory devices by maintaining the integrity of the transistor characteristics.
Implementation Method 1
a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess
Data Source
AI summary
An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.