3D Memory Kerf Staircase Structure for Stress Relief
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Solution Overview
Problem
Semiconductor storage devices with three-dimensional memory cell arrays often experience crystal defects in the substrate between the memory cell array and the peripheral region, known as the kerf region, due to stress differences.
Innovation Solution
The implementation of a semiconductor storage device design that includes a substrate with alternately stacked insulating and conductive layers forming a staircase pattern, along with columnar portions and slits, which helps to alleviate stress by mirroring the configuration of the memory cell array in the kerf region, thereby preventing crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell array is implemented, then storage capacity is improved, but crystal defects appear in the substrate due to stress differences
Solution Approach 1:
The substrate is divided into a memory cell array region and a kerf region, with the staircase pattern selectively applied to the kerf region to segment the stress distribution and prevent crystal defects while maintaining high storage capacity in the memory cell array
Solution Approach 2:
The staircase pattern is applied locally only to the kerf region rather than the entire substrate, creating different structural qualities in different regions: the memory cell array maintains its standard structure for high storage capacity, while the kerf region gets the stress-alleviating staircase pattern to prevent crystal defects
2Productivity
If the memory cell array is densely packed, then productivity is improved, but stress concentration occurs in the kerf region
Solution Approach 1:
The staircase pattern introduces a vertical dimension to the kerf region structure, creating multiple terraced levels that distribute stress vertically and laterally, thereby reducing stress concentration in the kerf region while allowing the memory cell array to maintain high density
Data Source
AI summary
A semiconductor storage device includes a substrate, a first stacked body provided above the substrate and having a side portion configured in a staircase pattern, a plurality of columnar portions passing through the first stacked body, a second stacked body provided in an outer edge portion of the substrate, and a plurality of first slits. The first stacked body include a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked. The second stacked body includes the plurality of first insulating layers and the plurality of conductive layers that are alternately stacked. The plurality of first slits extends through the first and second stacked bodies in a direction intersecting a stacking direction of the first stacked body.