Memory Controller Key Change for Low-Latency Logical Erase

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Solution Overview

Problem

Existing memory devices face challenges in quickly and securely erasing data, especially in mobile devices, where power and resource constraints require efficient erase operations that prevent data recovery by the host.

Innovation Solution

Implementing a method that changes the encryption key used for encrypting meta-data fields and logical to physical maps during an erase operation, ensuring that data becomes unrecoverable by altering the encryption key, rather than physically destroying the data, which allows for faster erase operations with minimal additional circuitry and bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If physical data destruction is used for erase operations, then data security is improved, but erase time and power consumption increase

Engineering Contradiction:
Improvedata securityVSAvoiderase time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent uses encryption keys as a logical copy/protection mechanism rather than physically destroying data. By changing the encryption key, the data becomes unrecoverable without actual physical erasure, thus achieving secure erase rapidly without time-consuming physical destruction operations

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent changes the encryption key parameter to achieve data erasure. Instead of physically altering or destroying the data bits, the system changes the cryptographic parameter (encryption key) that protects the data, making it effectively erased from the host's perspective while avoiding slow physical erasure processes

Inventive Principle:
Principle #35Parameter changes

2Reliability

If physical data destruction is used for erase operations, then data security is improved, but power consumption increases

Engineering Contradiction:
Improvedata securityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the encryption key parameter instead of performing energy-intensive physical erasure operations. This parameter change approach consumes significantly less power while achieving the same security outcome of making data unrecoverable

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system uses cryptographic copying/protection mechanisms (encryption keys) rather than physical destruction. This allows secure data erasure through key management operations that are far more energy-efficient than physical erasure methods

Inventive Principle:
Principle #26Copying

3Productivity

If encryption key changing is used for erase operations, then erase speed is improved, but device complexity increases

Engineering Contradiction:
Improveerase speedVSAvoidcircuitry complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The encryption key management system serves multiple functions: it provides data security during normal operation and enables rapid erase operations when needed. This multi-functionality achieves fast erasure without requiring separate dedicated erasure circuitry, thus avoiding increased device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Use of energy by moving object

If encryption key changing is used for erase operations, then power consumption is reduced, but additional circuitry is required

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuitry requirements
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The encryption key management infrastructure performs dual roles: protecting data during normal operation and enabling fast erasure by key change. This eliminates the need for separate erasure circuitry, achieving low power consumption without increasing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11815939B2Low cost and low latency logical unit erase
Publication Date: 2023.11.14 LODESTAR LICENSING GROUP LLC
  • US11815939B2 patent drawing
  • US11815939B2 patent drawing
  • US11815939B2 patent drawing

AI summary

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.