Memory L2P Mapping with Dual-Address Encoding for Low-Latency Reads
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Solution Overview
Problem
Memory devices face challenges in managing large capacities where logical-to-physical (L2P) tables become too big to store locally, leading to increased read latency due to multiple accesses for multi-page data retrieval, especially in systems lacking on-chip DRAM like Universal Flash Storage (UFS) devices.
Innovation Solution
Implement dual address encoding in L2P tables by packing multiple physical addresses into a single entry, allowing host devices to retrieve data efficiently using a single read command, while maintaining compatibility with existing systems through duplicate entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If L2P tables are made larger to support high-capacity memory devices, then storage capacity is improved, but read latency increases due to multiple accesses for multi-page data retrieval
Solution Approach 1:
The patent introduces a dual-address encoding scheme that adds a new dimension to the L2P table structure. Instead of storing only single physical addresses per entry, the system encodes multiple physical addresses (up to 64) into a single entry using a compact representation. This dimensional expansion allows the L2P table to provide multi-page data retrieval capability without increasing the number of table entries, thereby reducing read latency while supporting high-capacity storage.
Solution Approach 2:
The patent segments the physical address space into multiple pages and organizes them in a hierarchical structure. The L2P table entries are segmented to represent multiple physical addresses through dual-address encoding, allowing efficient retrieval of multi-page data. This segmentation enables the system to handle large-capacity memory devices by breaking down the addressing complexity into manageable segments that can be efficiently managed and retrieved.
2Quantity of substance
If L2P tables store more entries to map larger address spaces, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The dual-address encoding scheme adds a new dimension to how physical addresses are represented in the L2P table. By encoding multiple physical addresses into a single entry using a compact dual-address format, the system can support large address spaces without proportionally increasing the number of table entries. This dimensional approach reduces the complexity of L2P table management while maintaining support for high-capacity storage devices.
Solution Approach 2:
The L2P table entries are designed with multi-functionality through dual-address encoding, where each entry can represent multiple physical addresses simultaneously. This universal encoding scheme allows the same L2P table structure to handle various storage capacities and address space requirements without requiring separate management mechanisms for different scenarios, thereby reducing overall device complexity.
3Loss of time
If single read commands are used to retrieve multiple pages of data, then read latency is reduced, but compatibility with existing systems deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-encoding multiple physical addresses into L2P table entries using dual-address encoding before data retrieval operations. This preliminary preparation allows the system to retrieve multiple pages of data in a single read command by providing the host with the encoded address information in advance. The pre-encoded structure enables efficient multi-page retrieval while maintaining compatibility with existing systems that expect standard address formats.
Solution Approach 2:
The dual-address encoding scheme creates a copied or extended representation of physical addresses that can be interpreted by both legacy and advanced systems. The encoding maintains compatibility with existing address formats while adding the capability to represent multiple addresses, allowing the system to retrieve multiple pages in a single command without breaking compatibility with older systems that use simpler address schemes.
Data Source
AI summary
Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.