Semiconductor Memory Ladder Architecture Reducing Current Path Length
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently laying out cell blocks to optimize memory cell access and reduce the impact of grain boundaries in semiconductor films, leading to insufficient cell current for read/write operations.
Innovation Solution
The semiconductor memory device employs a ladder connection type memory architecture, where cell blocks are arranged in a two-dimensional state with multiple sub-cell blocks connected in parallel between local bit lines and local source lines, each containing resistance change elements and cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If cell blocks are arranged in a conventional manner, then the layout is simple, but the current path length through the semiconductor film becomes long resulting in insufficient cell current for read/write operations
Solution Approach 1:
The cell array is divided into multiple cell blocks (first cell block, second cell block, etc.) arranged in the word line direction. Each cell block contains memory cells connected between a bit line and a local source line, with selection transistors controlled by selection gate lines. This segmentation creates multiple parallel current paths through the semiconductor film, reducing the effective current path length and ensuring sufficient cell current for read/write operations.
Solution Approach 2:
The patent introduces a three-dimensional structure where cell blocks are stacked in the word line direction with selection gate lines extending in the bit line direction. This dimensional arrangement creates multiple parallel current paths through the semiconductor film in different spatial dimensions, reducing the current path length and improving cell current sufficiency without increasing the planar area.
2Reliability
If cell blocks are arranged to reduce current path length, then cell current sufficiency is improved, but the layout complexity increases
Solution Approach 1:
The selection gate lines serve multiple functions: they control the selection transistors in different cell blocks, provide current paths through the semiconductor film, and enable read/write operations across multiple memory cells simultaneously. This multi-functionality reduces the need for additional control structures, maintaining layout simplicity while ensuring cell current sufficiency.
Solution Approach 2:
Multiple cell blocks are merged into a single array structure sharing common bit lines and source lines. The selection gate lines are shared across multiple cell blocks, and the current paths through the semiconductor film are combined into parallel pathways. This merging approach reduces overall layout complexity while maintaining sufficient cell current through the segmented current paths.
3Ease of manufacture
If conventional cell block arrangement is used, then manufacturing is simpler, but heat dissipation efficiency is reduced
Solution Approach 1:
The cell array is segmented into multiple cell blocks with independent current paths through the semiconductor film. This segmentation creates multiple heat dissipation pathways from the memory cells to the bit lines and source lines, improving heat dissipation efficiency while maintaining manufacturing simplicity through standardized cell block replication.
Data Source
AI summary
According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.