Memory Cell Landing Pad Layout for Reliable Buried Contacts
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Solution Overview
Problem
The increasing complexity of manufacturing semiconductor memory devices due to the need for high integration density and reduced design rules complicates the process of connecting components, leading to difficulties in ensuring reliable electrical connections between landing pads and buried contacts.
Innovation Solution
A semiconductor memory device design featuring a hexagonal array structure for landing pads and storage nodes, with central points connected by scalene triangles and equilateral triangles respectively, using extreme ultraviolet (EUV) lithography to form landing pads without pattern density-increasing techniques, enhancing the overlap margin and gap-fill characteristics for improved electrical connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules for configurations are reduced to achieve higher integration density, then the integration density is improved, but the process difficulty of connecting components increases
Solution Approach 1:
The landing pads are arranged in a non-equidistant hexagonal pattern where three adjacent landing pads form a scalene triangle with sides of different lengths (first side = 3F, second side < 3F, third side > 3F). This asymmetric arrangement optimizes the connection paths between bit lines and active regions, improving manufacturability while maintaining high integration density.
2Quantity of substance
If design rules for configurations are reduced to achieve higher integration density, then the integration density is improved, but the reliability of connection between components deteriorates
Solution Approach 1:
The asymmetric scalene triangle arrangement of landing pads with specifically controlled side lengths ensures reliable electrical connections. The varying side lengths (3F, <3F, >3F) provide optimized connection paths that maintain connection reliability even at reduced design rules.
Solution Approach 2:
The landing pads extend in the vertical direction onto the bit line structures, creating a three-dimensional connection path. This dimensional approach enhances connection reliability by providing multiple contact points and longer connection paths, compensating for the reduced lateral dimensions.
3Manufacturing precision
If conventional lithography techniques are used, then the manufacturing process becomes complex with pattern density-increasing techniques, but the precision of landing pad formation can be maintained
Solution Approach 1:
The invention uses extreme ultraviolet (EUV) lithography, which operates at a different wavelength parameter (13.5 nm) compared to conventional lithography. This parameter change enables direct formation of the complex hexagonal landing pad pattern without requiring additional pattern density-increasing techniques, simplifying the manufacturing process while maintaining precision.
Data Source
AI summary
A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.