Memory Latch Blocking Circuit for Power Reduction
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Solution Overview
Problem
Current memory devices face challenges in achieving high performance and low power consumption, particularly in mobile devices like tablets and smartphones, where efficient data storage and retrieval are required without excessive power usage.
Innovation Solution
The implementation of a memory device with a shared latch and blocking circuits that selectively block signal transmission during a lock time section, allowing for reduced power consumption and improved performance by masking latches and controlling data output based on a clock signal, along with a bitwise enabler for selective data writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuous data writing to all latches is performed, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent applies partial action by enabling only specific latches that need to store data while keeping other latches disabled. The bitwise enabler circuit selectively activates individual latches based on write enable signals, so that data writing operations are performed only on necessary portions of the latch array rather than all latches simultaneously. This reduces power consumption while maintaining productivity for the required data storage operations.
2Reliability
If signal transmission to all latches is continuous, then reliability is improved, but use of energy increases
Solution Approach 1:
The blocking circuit selectively blocks signal transmission to latches that are not currently active or do not require data updates. By controlling the timing and scope of signal transmission, the system maintains reliable data storage in active latches while avoiding unnecessary power consumption from transmitting signals to inactive latches during lock time sections.
3Productivity
If all latches are actively updated, then productivity is improved, but loss of energy increases
Solution Approach 1:
The bitwise enabler circuit implements partial action by updating only the specific latches that contain valid write data, rather than forcing updates to all latches in the array. This selective updating approach maintains high productivity for the required data operations while minimizing energy loss by avoiding unnecessary write operations to inactive latches.
4Use of energy by moving object
If blocking circuits are added to control signal transmission, then use of energy decreases, but device complexity increases
Solution Approach 1:
The blocking circuit functionality is merged with the existing latch structure and control logic. The bitwise enabler signals are integrated into the existing data writing control mechanism, combining the blocking function with the latch enable/disable capability. This merging approach reduces the need for separate blocking components and minimizes the increase in device complexity while achieving effective power control.
Data Source
AI summary
A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.