Semiconductor Memory Device Multivalued Data Latch Circuit
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Solution Overview
Problem
As the number of threshold voltages stored in a single memory cell increases in NAND flash memory, the number of latch circuits required also increases, leading to a decrease in writing speed, making it challenging to achieve high-speed data storage while minimizing the number of latch circuits.
Innovation Solution
A semiconductor memory device with a memory cell array connected to word lines and bit lines, featuring a data storage circuit with a combination of static and dynamic latch circuits, and control circuits that manage threshold voltages and data positioning to optimize writing speed without increasing the number of latch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of threshold voltages stored in a single memory cell increases to store more bits of data, then the data storage capacity is improved, but the number of latch circuits required increases causing writing speed to decrease
Solution Approach 1:
The patent segments the data storage function by separating the latch circuit from the memory cell. The latch circuit stores control signals (row address, column address, write data) while the memory cell stores the actual multivalued data. This segmentation allows the system to handle multiple threshold voltages without proportionally increasing the number of latch circuits, as the single latch circuit can sequence through multiple write operations.
Solution Approach 2:
The patent applies preliminary action by pre-loading the latch circuit with control signals (row address, column address, write data) before the actual write operation to the memory cell. The latch circuit holds these control signals ready, and when a write command is received, it sequentially provides the control signals to drive the write operation. This preparation in advance enables high-speed writing even when multiple threshold voltages are involved.
2Quantity of substance
If the number of latch circuits is increased to store multiple bits of data, then the data storage capability is improved, but the device complexity increases
Solution Approach 1:
The patent makes the single latch circuit universal by enabling it to store multiple types of control signals (row address, column address, write data) and to support multiple write operations for setting different threshold voltages. This multi-functional latch circuit replaces what would otherwise require multiple dedicated latch circuits, one for each threshold voltage level, thereby reducing device complexity while maintaining data storage capability.
Solution Approach 2:
The patent introduces dynamics by making the latch circuit's storage content changeable over time. Instead of having fixed latch circuits dedicated to specific threshold voltages, the latch circuit dynamically loads and stores different control signals as needed for different write operations. This dynamic reusability allows a single latch circuit to perform the work of multiple static latch circuits.
3Manufacturing precision
If more latch circuits are used to manage multiple threshold voltages, then the threshold voltage control capability is improved, but the writing speed decreases
Solution Approach 1:
The latch circuit pre-stores the control signals required for setting multiple threshold voltages (row address, column address, write data) before the write operation begins. When writing to set 2k threshold voltages, the latch circuit sequentially provides these control signals without requiring additional latch circuits for each voltage level. This preliminary preparation enables precise threshold voltage control while maintaining high writing speed.
Solution Approach 2:
The patent segments the control signal generation function from the threshold voltage setting function. The latch circuit is responsible for storing and sequencing control signals, while the memory cell and its associated write circuitry handle the actual threshold voltage setting. This functional segmentation allows precise control of multiple threshold voltages through a single latch circuit that sequentially provides the necessary control signals.
Data Source
AI summary
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.