Semiconductor Memory Device Latch Circuit Data Exchange
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in data write operations due to the need for repeated program and verify cycles, which can lead to increased power consumption and potential data loss, especially when handling multi-bit data storage.
Innovation Solution
The implementation of a semiconductor memory device with multiple latch circuits allows for data exchange between them during specific verify operations, optimizing the application of pre-charge voltages based on stored data, thereby reducing power consumption and ensuring data integrity by selectively applying voltages only to necessary bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-charge voltages are applied to all bit lines during verify operations, then data verification can be performed, but power consumption increases due to unnecessary voltage applications
Solution Approach 1:
The patent applies pre-charge voltages selectively only to specific bit lines where data exchange is required, rather than uniformly to all bit lines. The sense amplifier controls voltage application based on data states, applying pre-charge voltages only to bit lines connected to memory cells undergoing verify operations, thereby reducing unnecessary power consumption while maintaining verification accuracy.
Solution Approach 2:
Instead of applying pre-charge voltages to all bit lines (excessive action), the patent applies them only to the necessary subset of bit lines (partial action). The sense amplifier determines which bit lines require pre-charge based on the data exchange requirements, applying voltages only where needed for the verify operation, thus avoiding waste while ensuring proper verification.
2Use of energy by moving object
If data is exchanged between latch circuits during verify operations, then power consumption is reduced, but data integrity may be compromised without proper restore operations
Solution Approach 1:
The patent performs data restore operations in advance or in conjunction with data exchange between latch circuits. Before or during the verify operation, the sense amplifier prepares the latch circuits by restoring data from the first latch circuit to the second latch circuit, ensuring data integrity is maintained while enabling power-efficient selective voltage application during the verify operation.
Solution Approach 2:
The sense amplifier uses feedback control to manage data exchange between latch circuits. Based on the state of data in the latch circuits and the requirements of the verify operation, the sense amplifier dynamically controls when and how data is exchanged and restored, ensuring that data integrity is maintained while optimizing power consumption through selective operations.
3Measurement precision
If multiple verify operations are performed for multi-bit data, then data accuracy improves, but operation time increases due to repeated loops
Solution Approach 1:
The patent divides the verify operation into segmented phases corresponding to different data bits. For multi-bit data storage, the verify operation is split into multiple targeted verify operations, each handling specific bit positions. The sense amplifier manages data exchange between latch circuits in a segmented manner, verifying different bits in organized stages, which improves data accuracy while optimizing the time required compared to unsegmented repeated loops.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell electrically coupled to the first bit line; and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.