Memory Device Latch for Data I/O Line Leakage Control
Solution Overview
Problem
Semiconductor memory devices consume unnecessary leakage current when in an inactive state due to the logic level of data previously latched by the latch unit, leading to increased direct current (DC) consumption as the devices operate more rapidly.
Innovation Solution
Incorporating a charging unit and a discharging unit within the semiconductor memory device to control the data I/O line when in an inactive state, with a selection unit to selectively drive either the pull-up or pull-down latch unit, reducing leakage current by charging or discharging the line based on current flow comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch unit maintains the logic level of previously latched data on the data I/O line during inactive state, then the data I/O line is prevented from floating and coupling, but unnecessary leakage current is consumed by the data I/O line and latch unit
Solution Approach 1:
The patent applies dynamics by making the latch unit's behavior state-dependent. The latch unit dynamically changes its function based on whether the memory device is in active or inactive state. During inactive state, the latch unit is controlled to discharge the data I/O line to ground, changing from maintaining logic levels to actively resetting them, thereby adapting to the different operational requirements and reducing unnecessary current consumption while maintaining reliability.
Solution Approach 2:
The patent changes the operational parameter of the latch unit based on the device state. By detecting the inactive state through control signals, the latch unit transitions from holding logic levels to discharging the data I/O line to a known state (ground). This parameter change allows the system to maintain the prevention of floating and coupling through a different mechanism (active discharge rather than passive holding), thereby eliminating the energy loss associated with maintaining logic levels during inactive periods.
2Productivity
If the semiconductor memory device operates rapidly with more data I/O lines, then the productivity and data transfer capability are improved, but the unnecessary current consumption by global data I/O lines and latch units increases
Solution Approach 1:
The patent applies dynamics by making the latch unit's behavior state-dependent. The latch unit dynamically changes its function based on whether the memory device is in active or inactive state. During inactive state, the latch unit is controlled to discharge the data I/O line to ground, changing from maintaining logic levels to actively resetting them, thereby adapting to the different operational requirements and reducing unnecessary current consumption while maintaining reliability.
Solution Approach 2:
The patent implements periodic action through the cyclic operation of charging and discharging the data I/O line during inactive states. The control unit periodically activates the discharge mechanism to reset the latch unit's output to ground, creating a rhythmic pattern of maintaining logic levels during active periods and discharging during inactive periods. This periodic action ensures that the system maintains data integrity when needed while eliminating unnecessary current consumption during idle periods, thereby improving the overall energy efficiency of rapid operations.
Data Source
AI summary
A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.