Memory Input Latch Circuit With DFE Feedback for Logic Detection

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in accurately determining the logic level of input signals due to signal degradation during transmission, particularly in high-speed communication scenarios, leading to incorrect data interpretation.

Innovation Solution

The implementation of decision feedback equalizer (DFE) circuits and latch circuits that utilize a reference voltage to determine the logic level of input signals, with feedback mechanisms to improve signal waveform quality and ensure accurate data interpretation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If signal transmission speed is increased for high-speed communication, then communication efficiency is improved, but signal degradation occurs leading to incorrect logic level determination

Engineering Contradiction:

Improvecommunication speedVSAvoiddata interpretation accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements a decision feedback equalizer that uses feedback signals from previously decided data to compensate for signal degradation. The feedback equalizer generates compensation signals based on past decisions and subtracts intersymbol interference from the current received signal, enabling accurate logic level determination even at high transmission speeds where signal degradation would otherwise cause errors

Inventive Principle:

Principle #23Feedback

2Device complexity

If conventional threshold comparison is used for logic level determination, then circuit simplicity is maintained, but signal degradation causes incorrect data interpretation

Engineering Contradiction:

Improvecircuit simplicityVSAvoidlogic level determination accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces a decision feedback equalizer as an intermediary component between the signal reception and threshold comparison stages. This equalizer pre-processes the degraded signal by removing intersymbol interference using feedback from previous decisions, thereby improving the quality of the signal before it reaches the simple threshold comparator, achieving both accuracy and simplicity

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12518830B2Semiconductor memory device

Publication Date: 2026.01.06 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.