Semiconductor Memory On-Chip Compare Latch Circuit Fail Bit Detection
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Solution Overview
Problem
Existing semiconductor memory devices with on-chip comparison functions are limited in detecting fail bits that can be replaced using antifuses like capacitance fuses, as the circuit configuration latches the first bit fail, preventing detection of chips that can be replaced by these antifuses.
Innovation Solution
A semiconductor memory device with an enhanced on-chip compare circuit and latch circuit that allows latching of fail bits other than the first bit, enabling detection of fail bits that can be remedied by antifuses such as capacitance fuses by receiving a second control signal to select whether the first fail bit or subsequent fail bits are latched.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the on-chip compare latch circuit latches the first bit fail due to circuit configuration, then the fail detection function is simplified, but the ability to detect chips that can be replaced by antifuses is lost
Solution Approach 1:
The latch circuit is divided into multiple independent latch units, each responsible for latching a specific bit's fail state. This segmentation allows the circuit to detect and latch fail bits at different positions without being constrained by a single first-bit-latching configuration, thereby enabling detection of antifuse-replaceable chips while maintaining manageable circuit complexity
Solution Approach 2:
The latch circuit incorporates dynamic control signals that enable or disable specific latch units based on the detected fail bit position. This dynamic behavior allows the circuit to adapt its latching function to different fail scenarios, ensuring that only relevant fail bits are latched while maintaining the ability to identify chips suitable for antifuse replacement
2Speed
If the latch circuit outputs latched fail information immediately, then the test speed is improved, but the ability to distinguish between first bit fails and subsequent bit fails is reduced
Solution Approach 1:
The latch circuit is segmented into multiple independent latch units, each associated with a specific bit position. Each latch unit independently latches the fail state of its corresponding bit, allowing the circuit to simultaneously maintain fast testing while preserving precise identification of fail bit positions through the segmented architecture
Solution Approach 2:
The circuit introduces intermediary signal lines that carry information about the latched fail state to external test equipment. These intermediary signals enable the test system to receive and process fail information quickly while the internal latch units maintain the association between specific bit positions and their fail states, thus preserving measurement precision
Data Source
AI summary
Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not the signals coincide with each other, to output the result of latching of the fail information based on a control signal. The latch circuit latches and outputs the fail information of a preset number bit output from the compare circuit during the time when a control signal for latching and outputting the fail information is in active state.