Nonvolatile Memory Controller Latch Pipeline for Read Efficiency
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Solution Overview
Problem
Current nonvolatile memory systems require multiple read operations to retrieve multi-bit data from multi-level cells, leading to inefficiencies and performance degradation due to idle times and peak current fluctuations during data output.
Innovation Solution
A nonvolatile memory system and method that utilize a controller with multiple latches to perform single program and read operations for multi-bit data, where data is sequentially latched and output in a pipelined manner, reducing the need for multiple read operations and minimizing peak current fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple read operations are used to retrieve multi-bit data from multi-level cells, then data can be completely read out, but idle times increase and performance degrades
Solution Approach 1:
The patent applies preliminary action by latching all M-bit data from the multi-level cell into M latches during a first half read period before the actual data output begins. This pre-loading of data into latch circuits eliminates the need for multiple sequential read operations, as all data is prepared in advance for simultaneous or sequential output during the second half read period, thereby eliminating idle times and improving data retrieval efficiency
Solution Approach 2:
The patent segments the data storage and output process by dividing M-bit data into M separate latches, where each latch holds one bit. This segmentation allows the controller to manage and output data bits in an organized sequence during the second half read period without requiring multiple complete read operations, thus reducing idle time while maintaining complete data retrieval
2Reliability
If multiple read operations are performed to output multi-bit data, then all data is retrieved, but peak current fluctuations increase
Solution Approach 1:
By latching all M-bit data into M latches during the first half read period before output begins, the patent prepares all data in advance with a single read operation. This eliminates the need for multiple sequential read operations that would cause repeated peak current fluctuations, thereby stabilizing current consumption while ensuring complete and reliable data output during the second half read period
Solution Approach 2:
The patent establishes continuity of useful action by performing the entire data latching operation in one continuous process during the first half read period, followed by continuous data output during the second half read period. This eliminates the interruptions and repeated start-stop cycles of multiple read operations, resulting in smoother current consumption and reduced peak fluctuations while maintaining reliable data retrieval
3Productivity
If single program operation is used to program multi-bit data, then programming efficiency improves, but complex latch control is required
Solution Approach 1:
The patent segments M-bit data into M separate latches, with each latch receiving and holding one bit of data during the first half program period. This segmentation enables the controller to systematically manage the programming process by controlling each latch individually, achieving single-program-operation efficiency while maintaining manageable control complexity through structured organization
Solution Approach 2:
The patent applies preliminary action by latching all M-bit data into M latches during the first half program period before the actual programming of the multi-level cell begins. This pre-latching approach enables single-program-operation efficiency, as the cell is programmed once with all data already prepared in the latches, while the control complexity is managed through the systematic sequential latching process
4Productivity
If sequential latching of M-bit data into M latches is performed, then single read operation is enabled, but more latch circuits are required
Solution Approach 1:
The patent segments M-bit data into M separate latches, with each latch dedicated to holding one bit. This segmentation enables the system to retrieve all M bits in a single read operation by reading from all latches simultaneously or sequentially, achieving high read efficiency. The trade-off of requiring M latch circuits is justified by the elimination of multiple read operations and the resulting improvement in productivity
Solution Approach 2:
The M latches serve multiple functions: they temporarily store M-bit data during the first half read period, enable single-read-operation efficiency, and facilitate organized sequential output during the second half read period. This multi-functionality justifies the use of M latch circuits, as they enable the controller to achieve single read operation efficiency while maintaining flexible and systematic data management
Data Source
AI summary
A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.