Latch System for Memory Circuit Banks
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Solution Overview
Problem
The existing latch system for memory circuits has unpredictable output signals due to simultaneous control of transmission gates by the latch enabling signal, leading to inefficiencies and area wastage.
Innovation Solution
A latch system design where a first transmission gate is controlled by a front latch enabling signal and a second transmission gate is controlled by a rear latch enabling signal, ensuring they are never on simultaneously, with a single front latch circuit and multiple rear latch circuits, each receiving an intermediate signal to generate a rear latch datum for corresponding banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single latch enabling signal controls both transmission gates simultaneously, then the control logic is simplified, but the output signal becomes unpredictable when the enabling signal transitions slowly
Solution Approach 1:
The patent divides the single latch enabling signal into two separate enabling signals: a front latch enabling signal for the first transmission gate and a rear latch enabling signal for the second transmission gate. This segmentation allows independent control of each transmission gate, preventing the simultaneous on-state that causes unpredictable output signals while maintaining manageable control logic through structured signal distribution.
2Reliability
If multiple front latch circuits are used to ensure reliable output, then the output reliability is improved, but the overall circuit area increases
Solution Approach 1:
The patent introduces an intermediate signal as a mediator between the front latch circuit and the rear latch circuits. The front latch circuit processes the input data and generates this intermediate signal, which is then distributed to multiple rear latch circuits. This intermediary approach ensures reliable signal distribution to multiple banks without requiring multiple front latch circuits, thereby maintaining output reliability while minimizing circuit area.
Data Source
AI summary
A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.