Memory Latch Circuitry With Unified Scan Chains for Area Reduction
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Solution Overview
Problem
Conventional semiconductor fabrication designs with embedded scan chains require significant area due to multiple signals and associated circuitry, necessitating a redesign to reduce the area footprint of integrated circuitry.
Innovation Solution
The implementation of latch circuitry that reduces the number of scan-shift chains by unifying scan chains in asynchronous read and write clock domains, merging signals like data, write enable, and read into a single scan chain, and reducing observability latches, thereby optimizing area efficiency in memory designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional embedded scan chains with full scan flip-flops are used for asynchronous clock design, then data capture and read operations can be performed, but the area footprint of the integrated circuitry increases significantly
Solution Approach 1:
The patent merges multiple scan chains (write data-in, write enable, and read data-out) into a unified scan chain structure. This consolidation reduces the number of separate flip-flops and associated circuitry required, thereby decreasing the area footprint while maintaining the functionality of data capture and read operations in asynchronous clock design
Solution Approach 2:
The unified scan chain is designed to perform multiple functions: it handles both write data capture and read data output operations. By making the scan chain multi-functional, the patent eliminates the need for separate dedicated scan chains for different operations, thus reducing overall area requirements while preserving reliability
2Reliability
If multiple scan chains are used to handle different signals (data, write enable, read), then signal integrity is maintained, but the device complexity increases
Solution Approach 1:
The patent combines multiple signal paths (data, write enable, read) into a single unified scan chain. This merging reduces the number of separate circuit paths and flip-flops required, thereby decreasing device complexity while maintaining signal integrity through careful timing and control mechanisms
Solution Approach 2:
Within the unified scan chain, the patent segments different signal types into distinct operational phases or zones. This segmentation allows different signals to be handled sequentially or in controlled parallelism, maintaining signal integrity while avoiding the complexity of fully separate dedicated chains for each signal type
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.