Non-volatile Memory Reading via Parallel Latch Voltage Averaging
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Solution Overview
Problem
Existing NAND-type non-volatile semiconductor memory devices face challenges in data reading due to insufficient sensing margin caused by Random Telegraph Signal noise, trapped charge transfer, instability in sensing circuits, and variations in reading-out voltage, leading to erroneous data retrieval.
Innovation Solution
A non-volatile semiconductor memory device and method utilizing an odd number of latch circuits with capacitors to selectively hold and parallelly connect voltages from multiple memory cell readings, determining data values by a majority rule based on composite voltages, thereby reducing circuit size and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple read-out operations are performed and averaged to improve data accuracy, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs multiple read-out operations and stores the results in latch circuits before final determination. By preparing multiple candidate values in advance through preliminary read operations, the system can quickly determine the majority value without performing multiple complete read cycles, thus reducing the time penalty while maintaining accuracy.
Solution Approach 2:
The patent replaces the conventional sequential averaging process with a parallel voltage comparison mechanism. Instead of sequentially reading, averaging, and comparing values, the system uses latch circuits to hold voltages and a majority determination circuit to simultaneously compare and determine the result, substituting mechanical sequential operations with electronic parallel processing.
2Measurement precision
If conventional sensing circuits are used to read memory cell data, then device complexity is kept simple, but measurement precision deteriorates due to insufficient sensing margin
Solution Approach 1:
The patent divides the sensing function into multiple independent latch circuits, each capable of holding a read-out voltage. This segmentation allows each latch to be simple in structure while the collective system achieves high precision through majority determination, resolving the contradiction between individual circuit simplicity and overall measurement precision.
Solution Approach 2:
The patent merges multiple latch circuit outputs into a majority determination circuit that combines their voltages. This merging process integrates the results from multiple simple latch circuits to produce a high-precision output, achieving enhanced sensing margin through the collective action of multiple simple components rather than a single complex circuit.
3Productivity
If logical operations are performed sequentially to determine majority rule, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The patent replaces sequential logical operations with a parallel voltage comparison mechanism. The majority determination circuit simultaneously compares voltages from multiple latch circuits and determines the result in one operation, substituting multi-step sequential logic with a single parallel electronic comparison process, thereby dramatically improving productivity.
Solution Approach 2:
The patent performs preliminary read-out operations and stores results in latch circuits before the final determination step. This preliminary action prepares all candidate values in advance, allowing the majority determination to be performed in a single quick operation rather than requiring multiple sequential logical steps, thus improving overall data retrieval speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly shortens data reading time and reduces circuit size by averaging voltages across multiple readings, enhancing data retrieval accuracy and efficiency compared to prior arts.
Implementation Method 1
each of which comprising a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence
Implementation Method 2
connecting the capacitor of each of the odd number of latch circuits in parallel after the capacitor of each of the odd number of latch circuits selectively holding the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and determining the data value by the majority rule based on a composite voltage of the capacitor of each of the odd number of latch circuits connected in parallel
Data Source
AI summary
In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel.