Memory Device Latching Circuitry Timing Consistency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face reliability issues when using Design For Test (DFT) techniques due to differences in operation between test and read modes, leading to inconsistent clock-to-output times and de-access times, which question the validity of test results.
Innovation Solution
A memory device design that includes latching circuitry, a shared path for both read and test modes, and control circuitry to manage the enable signal for consistent output timing, allowing the same enable signal to control both the detection of voltage changes and the output of latching values in both modes, thereby minimizing differences in clock-to-output times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate control signals are used for test mode and read mode operations, then test mode can be independently controlled, but clock-to-output times differ between modes reducing test reliability
Solution Approach 1:
The patent merges the control of test mode and read mode operations under a single enable signal. The enable signal simultaneously controls the latching circuitry in test mode and the sense amplifier in read mode, ensuring identical timing characteristics and clock-to-output times across both modes, thereby validating test results against actual operational behavior
Solution Approach 2:
The enable signal is designed to serve multiple functions: it controls the latching circuitry during test mode operations and controls the sense amplifier during read mode operations. This universal control mechanism ensures that both modes operate with identical timing characteristics, making the test mode a accurate representation of read mode behavior
2Ease of manufacture
If different circuit paths are used for test and read modes, then mode-specific optimization is possible, but timing inconsistencies arise between modes
Solution Approach 1:
The patent introduces a shared path as an intermediary between the latching circuitry and the output buffer that is used in both test mode and read mode. This shared path ensures that the timing characteristics and signal propagation delay are identical in both modes, eliminating timing inconsistencies while allowing mode-specific optimizations in the preceding circuit stages
3Productivity
If de-access time is optimized for read mode, then read performance improves, but test mode timing may become mismatched
Solution Approach 1:
The enable signal serves as a universal control that governs both the sense amplifier operation in read mode and the latching circuitry operation in test mode. By using the same control signal, the de-access time and overall timing characteristics are maintained consistently across both modes, ensuring that test mode timing accurately reflects read mode performance without requiring separate optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures more accurate testing of peripheral logic by maintaining similar clock-to-output times in both read and test modes, improving the reliability of DFT techniques and matching de-access times to access times without degrading performance.
Implementation Method 1
sensing circuitry to, when an enable signal is active, detect a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and to output said latching value on said path, wherein said latching value is dependent on said voltage change
Data Source
AI summary
A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path. Said latching circuitry outputs said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.