Semiconductor Memory Late Write Register Parallel RMW
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Solution Overview
Problem
Semiconductor memory devices with Read-Modify-Write (RMW) function experience performance degradation due to the need for multiple cycles to complete a write operation, which prolongs the selection state of the word line and increases memory access time.
Innovation Solution
Incorporating a correction bit generation circuit and a late write register to perform a dummy read, generate a data set, and write data in parallel, allowing for a late write operation that reduces the number of cycles required for a write command to be processed, thereby minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy read operation is performed before write operation to generate hamming code, then error correction function is maintained, but memory access time increases and performance degrades
Solution Approach 1:
The patent applies preliminary action by performing the dummy read operation before the actual write operation to prepare the memory core in a suitable state for receiving write data. This ensures that the error correction function is maintained without significantly delaying the write operation, as the preliminary read prepares necessary data and state in advance.
Solution Approach 2:
The patent merges the dummy read operation with the write operation by executing them in close temporal proximity and integrating their control logic. The dummy read is performed as part of the write sequence, and the selection signal timing is coordinated so that the read and write operations overlap or occur in succession without requiring separate independent cycles, thereby reducing overall access time.
2Measurement precision
If multiple cycles are used to complete write operation with RMW function, then data processing accuracy is improved, but device processing speed decreases
Solution Approach 1:
The patent applies dynamics by making the write operation process adaptable and flexible in terms of timing. The late write feature allows the write operation to be delayed until necessary, and the selection signal timing is dynamically adjusted based on the specific circumstances of the RMW operation, enabling the system to optimize between accuracy and speed on a case-by-case basis.
Solution Approach 2:
The patent performs preliminary actions (dummy read and data preparation) before the actual write operation, so that when the write occurs, the memory core is already in the appropriate state. This reduces the number of additional cycles needed and allows for more efficient processing while maintaining data processing accuracy.
3Reliability
If word line selection state is prolonged for RMW operation, then data integrity is ensured, but memory bandwidth utilization decreases
Solution Approach 1:
The patent merges the dummy read and write operations into a coordinated sequence where the word line selection is managed efficiently. The selection signal is activated for the dummy read, then immediately reused or reused in coordination with the write operation, reducing the total time the word line remains in selection state and improving memory bandwidth utilization while ensuring data integrity.
Solution Approach 2:
The patent ensures continuity of useful action by making the word line selection signal continuous or overlapping between the dummy read and write operations. Rather than having the selection signal go completely inactive between operations, it is maintained or reactivated in a way that keeps the memory core engaged in productive operations, thereby improving bandwidth utilization while maintaining data integrity.
Data Source
AI summary
Disclosed is a semiconductor memory device that includes a late write register for temporarily storing a late write address and late write data. When a write command is input, the semiconductor memory device performs a dummy read, creates a data set having a predetermined bit width from data read by the dummy read and write data, and generates a correction bit from the data set. In parallel with the generation of the data set and the generation of the correction bit, the semiconductor memory device not only performs a late write to write the late write data at the late write address in the memory core, but also stores a write address in the late write register as a new late write address and stores the data set and the correction bit in the late write register as new late write data.