Memory Command Latency Control for Bubble-Free Bank Operations
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Solution Overview
Problem
Existing semiconductor memory systems face inefficiencies due to command timing delays, data toggling issues causing DQ bubbles, and bank operation delays, which degrade performance and efficiency.
Innovation Solution
Implementing a memory device with on-the-fly (OTF) latency commands that include a command latency (CDL) value, allowing operations to be performed after a specified latency period, thereby optimizing command and bank efficiencies by minimizing idle states and data bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory controller issues a refresh command for another memory bank after issuing a read/write command, then the memory controller can maintain continuous operation, but command timing delay occurs for other banks and bank efficiency is degraded
Solution Approach 1:
The patent implements dynamic command latency adjustment by introducing variable latency values (e.g., 2CK, 3CK, 4CK) for different command types and bank states. The memory controller dynamically selects appropriate latency values based on current bank availability and command priority, allowing flexible timing optimization that resolves the conflict between continuous operation and minimal delay
Solution Approach 2:
The patent changes the parameter of command timing by introducing multiple latency modes (e.g., normal latency, reduced latency, zero latency) that can be selected based on operational requirements. This parameter variation allows the system to optimize between continuous operation and minimizing bank wait times by adjusting command execution timing
2Productivity
If the memory controller adjusts commands to ensure continuous data toggling without DQ bubbles, then data transfer efficiency is improved, but command idle states are generated and command efficiency is degraded
Solution Approach 1:
The patent applies partial action by transmitting only the necessary number of clock cycles for each command based on the specific operation requirements. Instead of maintaining continuous command transmission, the system transmits commands with precise timing based on actual data transfer needs, eliminating unnecessary command idle states while preventing DQ bubbles through targeted timing adjustments
3Speed
If the frequency of the data clock is set to an integer multiple of the system clock frequency (e.g., 4 times), then high-speed interface support is enabled, but command timing alignment becomes complex and requires precise synchronization
Solution Approach 1:
The patent segments the timing relationship between system clock and data clock by defining specific alignment points and phase relationships. The command timing is segmented into discrete intervals that align with both clock domains, using segmented latency values that are multiples of the system clock period, simplifying the synchronization complexity while maintaining high data clock frequencies
Data Source
AI summary
A memory device supporting OTF latency includes a plurality of signal pins connected to a plurality of signal lines; and a control logic circuit configured to receive an OTF command including a command latency (CDL) value indicating the OTF latency through command lines among the plurality of signal lines, and control an operation of the memory device to be performed based on the OTF latency and a time point at which the OTF command is applied.